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| author | Torbjörn SVENSSON <torbjorn.svensson@foss.st.com> | 2024-11-21 19:56:19 +0100 |
|---|---|---|
| committer | Torbjörn SVENSSON <torbjorn.svensson@foss.st.com> | 2024-12-12 12:25:19 +0100 |
| commit | e7615f6c99f93056b344ad07ee909114ee54f471 (patch) | |
| tree | c3dcf8221d4d2512321235b3be0f06091f59d530 /gcc | |
| parent | 09499ffbb3028f2db2dd97c2b764f0efe92bf3ef (diff) | |
| download | gcc-e7615f6c99f93056b344ad07ee909114ee54f471.zip gcc-e7615f6c99f93056b344ad07ee909114ee54f471.tar.gz gcc-e7615f6c99f93056b344ad07ee909114ee54f471.tar.bz2 | |
testsuite: arm: Use -mtune=cortex-m4 for thumb-ifcvt.c test
On Cortex-M4, the code generated is:
cmp r0, r1
itte ne
lslne r0, r0, r1
asrne r0, r0, #1
moveq r0, r1
add r0, r0, r1
bx lr
On Cortex-M7, the code generated is:
cmp r0, r1
beq .L3
lsls r0, r0, r1
asrs r0, r0, #1
add r0, r0, r1
bx lr
.L3:
mov r0, r1
add r0, r0, r1
bx lr
As Cortex-M7 only allow maximum one conditional instruction, force
Cortex-M4 to have a stable test case.
gcc/testsuite/ChangeLog:
* gcc.target/arm/thumb-ifcvt.c: Use -mtune=cortex-m4.
Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/thumb-ifcvt.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c b/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c index 02e56f5..c7786fa 100644 --- a/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c +++ b/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c @@ -1,7 +1,7 @@ /* Check that Thumb 16-bit shifts can be if-converted. */ /* { dg-do compile } */ /* { dg-require-effective-target arm_thumb2_ok } */ -/* { dg-options "-O2 -mthumb -mno-restrict-it" } */ +/* { dg-options "-O2 -mthumb -mtune=cortex-m4 -mno-restrict-it" } */ int foo (int a, int b) |