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| author | Haochen Jiang <haochen.jiang@intel.com> | 2025-07-11 16:16:52 +0800 |
|---|---|---|
| committer | Haochen Jiang <haochen.jiang@intel.com> | 2025-07-14 14:28:44 +0800 |
| commit | e69b78c9e2ba254dbc51d05e505159755bc7286e (patch) | |
| tree | b986cc6dc3a3d3e5d2dcbd24dd38a197a5cdcc4b /gcc | |
| parent | db3afff48fc7ed896b3dd17eb93f0cfe3cc41da8 (diff) | |
| download | gcc-e69b78c9e2ba254dbc51d05e505159755bc7286e.zip gcc-e69b78c9e2ba254dbc51d05e505159755bc7286e.tar.gz gcc-e69b78c9e2ba254dbc51d05e505159755bc7286e.tar.bz2 | |
i386: Remove KEYLOCKER related feature since Panther Lake and Clearwater Forest
According to July 2025 SDM, Key locker will no longer be supported on
hardware 2025 onwards. This means for Panther Lake and Clearwater Forest,
the feature will not be enabled. Remove them from those two platforms.
gcc/ChangeLog:
* config/i386/i386.h (PTA_PANTHERLAKE): Revmoe KL and WIDEKL.
(PTA_CLEARWATERFOREST): Ditto.
* doc/invoke.texi: Revise documentation.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/i386.h | 9 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 12 |
2 files changed, 11 insertions, 10 deletions
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 3f7ad68..bfc6c6f 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2465,10 +2465,11 @@ constexpr wide_int_bitmask PTA_ARROWLAKE = PTA_ALDERLAKE | PTA_AVXIFMA | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD | PTA_UINTR; constexpr wide_int_bitmask PTA_ARROWLAKE_S = PTA_ARROWLAKE | PTA_AVXVNNIINT16 | PTA_SHA512 | PTA_SM3 | PTA_SM4; -constexpr wide_int_bitmask PTA_CLEARWATERFOREST = PTA_SIERRAFOREST - | PTA_AVXVNNIINT16 | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_USER_MSR - | PTA_PREFETCHI; -constexpr wide_int_bitmask PTA_PANTHERLAKE = PTA_ARROWLAKE_S | PTA_PREFETCHI; +constexpr wide_int_bitmask PTA_CLEARWATERFOREST = + (PTA_SIERRAFOREST & (~(PTA_KL | PTA_WIDEKL))) | PTA_AVXVNNIINT16 | PTA_SHA512 + | PTA_SM3 | PTA_SM4 | PTA_USER_MSR | PTA_PREFETCHI; +constexpr wide_int_bitmask PTA_PANTHERLAKE = + (PTA_ARROWLAKE_S & (~(PTA_KL | PTA_WIDEKL))) | PTA_PREFETCHI; constexpr wide_int_bitmask PTA_DIAMONDRAPIDS = PTA_GRANITERAPIDS_D | PTA_AVXIFMA | PTA_AVXNECONVERT | PTA_AVXVNNIINT16 | PTA_AVXVNNIINT8 | PTA_CMPCCXADD | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_AVX10_2 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9a1aa37..f60865b 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -34892,9 +34892,9 @@ Intel Panther Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, -VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, UINTR, AVXIFMA, -AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4 and -PREFETCHI instruction set support. +VAES, VPCLMULQDQ, SERIALIZE, HRESET, AVX-VNNI, UINTR, AVXIFMA, AVXVNNIINT8, +AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4 and PREFETCHI +instruction set support. @item sapphirerapids @itemx emeraldrapids @@ -34997,9 +34997,9 @@ Intel Clearwater Forest CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, -LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, -ENQCMD, UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, -SHA512, SM3, SM4, USER_MSR and PREFETCHI instruction set support. +LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, AVX-VNNI, ENQCMD, +UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, +SM3, SM4, USER_MSR and PREFETCHI instruction set support. @item k6 AMD K6 CPU with MMX instruction set support. |