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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-05-31 18:47:03 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-05-31 21:51:02 +0800 |
| commit | e2a326227977dd361bb3b52b8409ebc57240a2a7 (patch) | |
| tree | 87d50625ac1ca824e96a90afff21394fd5791108 /gcc | |
| parent | 070d651c6db37c3658be0a5274f44265045428e6 (diff) | |
| download | gcc-e2a326227977dd361bb3b52b8409ebc57240a2a7.zip gcc-e2a326227977dd361bb3b52b8409ebc57240a2a7.tar.gz gcc-e2a326227977dd361bb3b52b8409ebc57240a2a7.tar.bz2 | |
RISC-V: Remove FRM for vfncvt.rod instruction
Apparently, vfncvt.rod rounding mode is encoded, so we don't need FRM.
gcc/ChangeLog:
* config/riscv/vector.md: Remove FRM.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/vector.md | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index cd696da..60f052b 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7290,10 +7290,8 @@ (match_operand 5 "const_int_operand" " i, i, i, i, i, i") (match_operand 6 "const_int_operand" " i, i, i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:<V_DOUBLE_TRUNC> [(float_truncate:<V_DOUBLE_TRUNC> (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD) |