[PATCH, GCC/ARM, 3/10] Save/restore FPCXTNS in nsentry functions

This patch consists mainly of creating 2 new instruction patterns to push and pop special FP registers via vldm and vstr and using them in prologue and epilogue. The patterns are defined as push/pop with an unspecified operation on the memory accessed, with an unspecified constant indicating what special FP register is being saved/restored. Other aspects of the patch include: * defining the set of special registers that can be saved/restored and their name * reserving space in the stack frames for these push/pop * preventing return via pop * guarding the clearing of FPSCR to target architecture not having Armv8.1-M Mainline instructions. *** gcc/ChangeLog *** 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 2020-01-16 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm.c (fp_sysreg_names): Declare and define. (use_return_insn): Also return false for Armv8.1-M Mainline. (output_return_instruction): Skip FPSCR clearing if Armv8.1-M Mainline instructions are available. (arm_compute_frame_layout): Allocate space in frame for FPCXTNS when targeting Armv8.1-M Mainline Security Extensions. (arm_expand_prologue): Save FPCXTNS if this is an Armv8.1-M Mainline entry function. (cmse_nonsecure_entry_clear_before_return): Clear IP and r4 if targeting Armv8.1-M Mainline or successor. (arm_expand_epilogue): Fix indentation of caller-saved register clearing. Restore FPCXTNS if this is an Armv8.1-M Mainline entry function. * config/arm/arm.h (TARGET_HAVE_FP_CMSE): New macro. (FP_SYSREGS): Likewise. (enum vfp_sysregs_encoding): Define enum. (fp_sysreg_names): Declare. * config/arm/unspecs.md (VUNSPEC_VSTR_VLDR): New volatile unspec. * config/arm/vfp.md (push_fpsysreg_insn): New define_insn. (pop_fpsysreg_insn): Likewise. *** gcc/testsuite/Changelog *** 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 2020-01-16 Thomas Preud'homme <thomas.preudhomme@arm.com> * gcc.target/arm/cmse/bitfield-1.c: add checks for VSTR and VLDR. * gcc.target/arm/cmse/bitfield-2.c: Likewise. * gcc.target/arm/cmse/bitfield-3.c: Likewise. * gcc.target/arm/cmse/cmse-1.c: Likewise. * gcc.target/arm/cmse/struct-1.c: Likewise. * gcc.target/arm/cmse/cmse.exp: Run existing Armv8-M Mainline tests from mainline/8m subdirectory and new Armv8.1-M Mainline tests from mainline/8_1m subdirectory. * gcc.target/arm/cmse/mainline/bitfield-4.c: Move into ... * gcc.target/arm/cmse/mainline/8m/bitfield-4.c: This. * gcc.target/arm/cmse/mainline/bitfield-5.c: Move into ... * gcc.target/arm/cmse/mainline/8m/bitfield-5.c: This. * gcc.target/arm/cmse/mainline/bitfield-6.c: Move into ... * gcc.target/arm/cmse/mainline/8m/bitfield-6.c: This. * gcc.target/arm/cmse/mainline/bitfield-7.c: Move into ... * gcc.target/arm/cmse/mainline/8m/bitfield-7.c: This. * gcc.target/arm/cmse/mainline/bitfield-8.c: Move into ... * gcc.target/arm/cmse/mainline/8m/bitfield-8.c: This. * gcc.target/arm/cmse/mainline/bitfield-9.c: Move into ... * gcc.target/arm/cmse/mainline/8m/bitfield-9.c: This. * gcc.target/arm/cmse/mainline/bitfield-and-union-1.c: Move and rename into ... * gcc.target/arm/cmse/mainline/8m/bitfield-and-union.c: This. * gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c: Move into ... * gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-13.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c: Move into ... * gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-5.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c: Move into ... * gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-7.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c: Move into ... * gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-8.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/hard/cmse-13.c: Move into ... * gcc.target/arm/cmse/mainline/8m/hard/cmse-13.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/hard/cmse-5.c: Move into ... * gcc.target/arm/cmse/mainline/8m/hard/cmse-5.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/hard/cmse-7.c: Move into ... * gcc.target/arm/cmse/mainline/8m/hard/cmse-7.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/hard/cmse-8.c: Move into ... * gcc.target/arm/cmse/mainline/8m/hard/cmse-8.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/soft/cmse-13.c: Move into ... * gcc.target/arm/cmse/mainline/8m/soft/cmse-13.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/soft/cmse-5.c: Move into ... * gcc.target/arm/cmse/mainline/8m/soft/cmse-5.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/soft/cmse-7.c: Move into ... * gcc.target/arm/cmse/mainline/8m/soft/cmse-7.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/soft/cmse-8.c: Move into ... * gcc.target/arm/cmse/mainline/8m/soft/cmse-8.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c: Move into ... * gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-5.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c: Move into ... * gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-7.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c: Move into ... * gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-8.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/softfp/cmse-13.c: Move into ... * gcc.target/arm/cmse/mainline/8m/softfp/cmse-13.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/softfp/cmse-5.c: Move into ... * gcc.target/arm/cmse/mainline/8m/softfp/cmse-5.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/softfp/cmse-7.c: Move into ... * gcc.target/arm/cmse/mainline/8m/softfp/cmse-7.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/softfp/cmse-8.c: Move into ... * gcc.target/arm/cmse/mainline/8m/softfp/cmse-8.c: This. Clean up dg-skip-if directive for float ABI. * gcc.target/arm/cmse/mainline/union-1.c: Move into ... * gcc.target/arm/cmse/mainline/8m/union-1.c: This. * gcc.target/arm/cmse/mainline/union-2.c: Move into ... * gcc.target/arm/cmse/mainline/8m/union-2.c: This. * gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c: New file. * gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c: New file. * gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c: New file. * gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c: New file. * gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c: New file. * gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c: New file. * gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c: New file. * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: New file. * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c: New file. * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: New file. * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: New file. * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: New file. * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c: New file. * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: New file. * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: New file. * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c: New file. * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c: New file. * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c: New file. * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c: New file. * gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c: New file. * gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c: New file. * gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c: New file. * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c: New file. * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c: New file. * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c: New file. * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c: New file. * gcc.target/arm/cmse/mainline/8_1m/union-1.c: New file. * gcc.target/arm/cmse/mainline/8_1m/union-2.c: New file. * lib/target-supports.exp (check_effective_target_arm_cmse_clear_ok): New procedure.
author: Mihail Ionescu <mihail.ionescu@arm.com> 2020-01-15 10:33:52 +0000
committer: Mihail Ionescu <mihail.ionescu@arm.com> 2020-01-16 15:11:15 +0000
commit: e0e4be48a9892195f11d1b608793c3a30b640f54 (patch)
tree: c76fd00b5769275e5ef1d80ce7f812d711acf098 /gcc
parent: e27cf2e372651997c3b46a5662dd4d47c53dd13b (diff)
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69 files changed, 947 insertions, 90 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d2d29cc..677a3ab 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,6 +1,30 @@
 2020-01-16  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
 2020-01-16  Thomas Preud'homme <thomas.preudhomme@arm.com>
 
+	* config/arm/arm.c (fp_sysreg_names): Declare and define.
+	(use_return_insn): Also return false for Armv8.1-M Mainline.
+	(output_return_instruction): Skip FPSCR clearing if Armv8.1-M
+	Mainline instructions are available.
+	(arm_compute_frame_layout): Allocate space in frame for FPCXTNS
+	when targeting Armv8.1-M Mainline Security Extensions.
+	(arm_expand_prologue): Save FPCXTNS if this is an Armv8.1-M
+	Mainline entry function.
+	(cmse_nonsecure_entry_clear_before_return): Clear IP and r4 if
+	targeting Armv8.1-M Mainline or successor.
+	(arm_expand_epilogue): Fix indentation of caller-saved register
+	clearing.  Restore FPCXTNS if this is an Armv8.1-M Mainline
+	entry function.
+	* config/arm/arm.h (TARGET_HAVE_FP_CMSE): New macro.
+	(FP_SYSREGS): Likewise.
+	(enum vfp_sysregs_encoding): Define enum.
+	(fp_sysreg_names): Declare.
+	* config/arm/unspecs.md (VUNSPEC_VSTR_VLDR): New volatile unspec.
+	* config/arm/vfp.md (push_fpsysreg_insn): New define_insn.
+	(pop_fpsysreg_insn): Likewise.
+
+2020-01-16  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
+2020-01-16  Thomas Preud'homme <thomas.preudhomme@arm.com>
+
 	* config/arm/arm-cpus.in (armv8_1m_main): New feature.
 	(ARMv4, ARMv4t, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6j, ARMv6k,
 	ARMv6z, ARMv6kz, ARMv6zk, ARMv6t2, ARMv6m, ARMv7, ARMv7a, ARMv7ve,
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index a7242b2..13633df 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -1021,6 +1021,12 @@ int arm_regs_in_sequence[] =
   0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
 };
 
+#define DEF_FP_SYSREG(reg) #reg,
+const char *fp_sysreg_names[NB_FP_SYSREGS] = {
+  FP_SYSREGS
+};
+#undef DEF_FP_SYSREG
+
 #define ARM_LSL_NAME "lsl"
 #define streq(string1, string2) (strcmp (string1, string2) == 0)
 
@@ -4245,8 +4251,9 @@ use_return_insn (int iscond, rtx sibling)
     }
 
   /* ARMv8-M nonsecure entry function need to use bxns to return and thus need
-     several instructions if anything needs to be popped.  */
-  if (saved_int_regs && IS_CMSE_ENTRY (func_type))
+     several instructions if anything needs to be popped.  Armv8.1-M Mainline
+     also needs several instructions to save and restore FP context.  */
+  if (IS_CMSE_ENTRY (func_type) && (saved_int_regs || TARGET_HAVE_FPCXT_CMSE))
     return 0;
 
   /* If there are saved registers but the LR isn't saved, then we need
@@ -20705,7 +20712,9 @@ output_return_instruction (rtx operand, bool really_return, bool reverse,
 			  "msr%s\tAPSR_nzcvq, %%|lr", conditional);
 
 	      output_asm_insn (instr, & operand);
-	      if (TARGET_HARD_FLOAT)
+	      /* Do not clear FPSCR if targeting Armv8.1-M Mainline, VLDR takes
+		 care of it.  */
+	      if (TARGET_HARD_FLOAT && ! TARGET_HAVE_FPCXT_CMSE)
 		{
 		  /* Clear the cumulative exception-status bits (0-4,7) and the
 		     condition code bits (28-31) of the FPSCR.  We need to
@@ -21997,6 +22006,11 @@ arm_compute_frame_layout (void)
       if (! IS_VOLATILE (func_type)
 	  && TARGET_HARD_FLOAT)
 	saved += arm_get_vfp_saved_size ();
+
+      /* Allocate space for saving/restoring FPCXTNS in Armv8.1-M Mainline
+	 nonecure entry functions with VSTR/VLDR.  */
+      if (TARGET_HAVE_FPCXT_CMSE && IS_CMSE_ENTRY (func_type))
+	saved += 4;
     }
   else /* TARGET_THUMB1 */
     {
@@ -22698,6 +22712,15 @@ arm_expand_prologue (void)
       RTX_FRAME_RELATED_P (insn) = 1;
     }
 
+  /* Armv8.1-M Mainline nonsecure entry: save FPCXTNS on stack using VSTR.  */
+  if (TARGET_HAVE_FPCXT_CMSE && IS_CMSE_ENTRY (func_type))
+    {
+      saved_regs += 4;
+      insn = emit_insn (gen_push_fpsysreg_insn (stack_pointer_rtx,
+						GEN_INT (FPCXTNS_ENUM)));
+      RTX_FRAME_RELATED_P (insn) = 1;
+    }
+
   if (args_to_push)
     {
       /* Push the argument registers, or reserve space for them.  */
@@ -26261,12 +26284,15 @@ cmse_nonsecure_entry_clear_before_return (void)
 
       bitmap_set_range (to_clear_bitmap, FIRST_VFP_REGNUM, float_bits);
 
-      /* Make sure we don't clear the two scratch registers used to clear the
-	 relevant FPSCR bits in output_return_instruction.  */
-      emit_use (gen_rtx_REG (SImode, IP_REGNUM));
-      bitmap_clear_bit (to_clear_bitmap, IP_REGNUM);
-      emit_use (gen_rtx_REG (SImode, 4));
-      bitmap_clear_bit (to_clear_bitmap, 4);
+      if (!TARGET_HAVE_FPCXT_CMSE)
+	{
+	  /* Make sure we don't clear the two scratch registers used to clear
+	     the relevant FPSCR bits in output_return_instruction.  */
+	  emit_use (gen_rtx_REG (SImode, IP_REGNUM));
+	  bitmap_clear_bit (to_clear_bitmap, IP_REGNUM);
+	  emit_use (gen_rtx_REG (SImode, 4));
+	  bitmap_clear_bit (to_clear_bitmap, 4);
+	}
     }
 
   /* If the user has defined registers to be caller saved, these are no longer
@@ -26876,12 +26902,23 @@ arm_expand_epilogue (bool really_return)
 				   stack_pointer_rtx, stack_pointer_rtx);
     }
 
-    /* Clear all caller-saved regs that are not used to return.  */
-    if (IS_CMSE_ENTRY (arm_current_func_type ()))
-      {
-	/* CMSE_ENTRY always returns.  */
-	gcc_assert (really_return);
-	cmse_nonsecure_entry_clear_before_return ();
+  if (IS_CMSE_ENTRY (func_type))
+    {
+      /* CMSE_ENTRY always returns.  */
+      gcc_assert (really_return);
+      /* Clear all caller-saved regs that are not used to return.  */
+      cmse_nonsecure_entry_clear_before_return ();
+
+      /* Armv8.1-M Mainline nonsecure entry: restore FPCXTNS from stack using
+	 VLDR.  */
+      if (TARGET_HAVE_FPCXT_CMSE)
+	{
+	  rtx_insn *insn;
+
+	  insn = emit_insn (gen_pop_fpsysreg_insn (stack_pointer_rtx,
+						   GEN_INT (FPCXTNS_ENUM)));
+	  RTX_FRAME_RELATED_P (insn) = 1;
+	}
       }
 
   if (!really_return)
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index e1cce23..182854f 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -315,6 +315,10 @@ emission of floating point pcs attributes.  */
 /* Nonzero if this chip provides the CBZ and CBNZ instructions.  */
 #define TARGET_HAVE_CBZ		(arm_arch_thumb2 || arm_arch8)
 
+/* Nonzero if this chip provides Armv8.1-M Mainline Security extensions
+   instructions (most are floating-point related).  */
+#define TARGET_HAVE_FPCXT_CMSE	(arm_arch8_1m_main)
+
 /* Nonzero if integer division instructions supported.  */
 #define TARGET_IDIV	((TARGET_ARM && arm_arch_arm_hwdiv)	\
 			 || (TARGET_THUMB && arm_arch_thumb_hwdiv))
@@ -1181,6 +1185,22 @@ enum reg_class
   { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F }  /* ALL_REGS */	\
 }
 
+#define FP_SYSREGS \
+  DEF_FP_SYSREG (FPSCR) \
+  DEF_FP_SYSREG (FPSCR_nzcvqc) \
+  DEF_FP_SYSREG (VPR) \
+  DEF_FP_SYSREG (P0) \
+  DEF_FP_SYSREG (FPCXTNS) \
+  DEF_FP_SYSREG (FPCXTS)
+
+#define DEF_FP_SYSREG(reg) reg ## _ENUM,
+enum vfp_sysregs_encoding {
+  FP_SYSREGS
+  NB_FP_SYSREGS
+};
+#undef DEF_FP_SYSREG
+extern const char *fp_sysreg_names[NB_FP_SYSREGS];
+
 /* Any of the VFP register classes.  */
 #define IS_VFP_CLASS(X) \
   ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index ade6b1a..40f6a8b 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -239,6 +239,7 @@
   VUNSPEC_MRRC2		; Represent the coprocessor mrrc2 instruction.
   VUNSPEC_SPECULATION_BARRIER ; Represents an unconditional speculation barrier.
   VUNSPEC_APSR_WRITE     ; Represent writing the APSR.
+  VUNSPEC_VSTR_VLDR	; Represent the vstr/vldr instruction.
 ])
 
 ;; Enumerators for NEON unspecs.
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index 28f2b77..a4f01e7 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -1599,6 +1599,44 @@
    (set_attr "type" "f_flag")]
 )
 
+(define_insn "push_fpsysreg_insn"
+  [(set (mem:SI (post_dec:SI (match_operand:SI 0 "s_register_operand" "+&rk")))
+   (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "n")]
+		       VUNSPEC_VSTR_VLDR))]
+  "TARGET_HAVE_FPCXT_CMSE && use_cmse"
+  {
+    static char buf[32];
+    int fp_sysreg_enum = INTVAL (operands[1]);
+
+    gcc_assert (IN_RANGE (fp_sysreg_enum, 0, NB_FP_SYSREGS - 1));
+
+    snprintf (buf, sizeof (buf), \"vstr%%?\\t%s, [%%0, #-4]!\",
+	      fp_sysreg_names[fp_sysreg_enum]);
+    return buf;
+  }
+  [(set_attr "predicable" "yes")
+   (set_attr "type" "store_4")]
+)
+
+(define_insn "pop_fpsysreg_insn"
+  [(set (mem:SI (post_inc:SI (match_operand:SI 0 "s_register_operand" "+&rk")))
+   (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "n")]
+		       VUNSPEC_VSTR_VLDR))]
+  "TARGET_HAVE_FPCXT_CMSE && use_cmse"
+  {
+    static char buf[32];
+    int fp_sysreg_enum = INTVAL (operands[1]);
+
+    gcc_assert (IN_RANGE (fp_sysreg_enum, 0, NB_FP_SYSREGS - 1));
+
+    snprintf (buf, sizeof (buf), \"vldr%%?\\t%s, [%%0], #4\",
+	      fp_sysreg_names[fp_sysreg_enum]);
+    return buf;
+  }
+  [(set_attr "predicable" "yes")
+   (set_attr "type" "load_4")]
+)
+
 (define_insn_and_split "*cmpsf_split_vfp"
   [(set (reg:CCFP CC_REGNUM)
 	(compare:CCFP (match_operand:SF 0 "s_register_operand"  "t")
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e6d2cd5..200b1cf 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,6 +1,124 @@
 2020-01-16  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
 2020-01-16  Thomas Preud'homme <thomas.preudhomme@arm.com>
 
+	* gcc.target/arm/cmse/bitfield-1.c: add checks for VSTR and VLDR.
+	* gcc.target/arm/cmse/bitfield-2.c: Likewise.
+	* gcc.target/arm/cmse/bitfield-3.c: Likewise.
+	* gcc.target/arm/cmse/cmse-1.c: Likewise.
+	* gcc.target/arm/cmse/struct-1.c: Likewise.
+	* gcc.target/arm/cmse/cmse.exp: Run existing Armv8-M Mainline tests
+	from mainline/8m subdirectory and new Armv8.1-M Mainline tests from
+	mainline/8_1m subdirectory.
+	* gcc.target/arm/cmse/mainline/bitfield-4.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/bitfield-4.c: This.
+	* gcc.target/arm/cmse/mainline/bitfield-5.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/bitfield-5.c: This.
+	* gcc.target/arm/cmse/mainline/bitfield-6.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/bitfield-6.c: This.
+	* gcc.target/arm/cmse/mainline/bitfield-7.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/bitfield-7.c: This.
+	* gcc.target/arm/cmse/mainline/bitfield-8.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/bitfield-8.c: This.
+	* gcc.target/arm/cmse/mainline/bitfield-9.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/bitfield-9.c: This.
+	* gcc.target/arm/cmse/mainline/bitfield-and-union-1.c: Move and rename
+	into ...
+	* gcc.target/arm/cmse/mainline/8m/bitfield-and-union.c: This.
+	* gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-13.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-5.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-7.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-8.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/hard/cmse-13.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/hard/cmse-13.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/hard/cmse-5.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/hard/cmse-5.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/hard/cmse-7.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/hard/cmse-7.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/hard/cmse-8.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/hard/cmse-8.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/soft/cmse-13.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/soft/cmse-13.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/soft/cmse-5.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/soft/cmse-5.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/soft/cmse-7.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/soft/cmse-7.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/soft/cmse-8.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/soft/cmse-8.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-5.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-7.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-8.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/softfp/cmse-13.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/softfp/cmse-13.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/softfp/cmse-5.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/softfp/cmse-5.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/softfp/cmse-7.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/softfp/cmse-7.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/softfp/cmse-8.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/softfp/cmse-8.c: This.  Clean up
+	dg-skip-if directive for float ABI.
+	* gcc.target/arm/cmse/mainline/union-1.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/union-1.c: This.
+	* gcc.target/arm/cmse/mainline/union-2.c: Move into ...
+	* gcc.target/arm/cmse/mainline/8m/union-2.c: This.
+	* gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/union-1.c: New file.
+	* gcc.target/arm/cmse/mainline/8_1m/union-2.c: New file.
+	* lib/target-supports.exp (check_effective_target_arm_cmse_clear_ok):
+	New procedure.
+
+2020-01-16  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
+2020-01-16  Thomas Preud'homme <thomas.preudhomme@arm.com>
+
 	* lib/target-supports.exp
 	(check_effective_target_arm_arch_v8_1m_main_ok): Define.
 	(add_options_for_arm_arch_v8_1m_main): Likewise.
diff --git a/gcc/testsuite/gcc.target/arm/cmse/bitfield-1.c b/gcc/testsuite/gcc.target/arm/cmse/bitfield-1.c
index 0fc191e..6d611e1 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/bitfield-1.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/bitfield-1.c
@@ -32,8 +32,10 @@ main (void)
   return 0;
 }
 
+/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" { target arm_cmse_clear_ok } } } */
 /* { dg-final { scan-assembler "movw\tr1, #1855" } } */
 /* { dg-final { scan-assembler "movt\tr1, 65535" } } */
 /* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */
+/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" { target arm_cmse_clear_ok } } } */
 /* { dg-final { scan-assembler "bxns" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/cmse/bitfield-2.c b/gcc/testsuite/gcc.target/arm/cmse/bitfield-2.c
index f8327c8..b7ec0a0 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/bitfield-2.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/bitfield-2.c
@@ -29,8 +29,10 @@ main (void)
   return 0;
 }
 
+/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" { target arm_cmse_clear_ok } } } */
 /* { dg-final { scan-assembler "movw\tr1, #1919" } } */
 /* { dg-final { scan-assembler "movt\tr1, 2047" } } */
 /* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */
+/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" { target arm_cmse_clear_ok } } } */
 /* { dg-final { scan-assembler "bxns" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/cmse/bitfield-3.c b/gcc/testsuite/gcc.target/arm/cmse/bitfield-3.c
index d0550db..7b9c3f0 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/bitfield-3.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/bitfield-3.c
@@ -30,8 +30,9 @@ main (void)
   return 0;
 }
 
+/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" { target arm_cmse_clear_ok } } } */
 /* { dg-final { scan-assembler "movw\tr1, #65535" } } */
 /* { dg-final { scan-assembler "movt\tr1, 63" } } */
 /* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */
+/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" { target arm_cmse_clear_ok } } } */
 /* { dg-final { scan-assembler "bxns" } } */
-
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c b/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c
index f764153..aa0ec8e 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c
@@ -104,6 +104,8 @@ qux (int_nsfunc_t * callback)
 /* { dg-final { scan-assembler "__acle_se_qux:" } } */
 /* { dg-final { scan-assembler "bic" } } */
 /* { dg-final { scan-assembler "push\t\{r4, r5, r6" } } */
+/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" { target arm_cmse_clear_ok } } } */
+/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" { target arm_cmse_clear_ok } } } */
 /* { dg-final { scan-assembler "msr\tAPSR_nzcvq" } } */
 
 int call_callback (void)
diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse.exp b/gcc/testsuite/gcc.target/arm/cmse/cmse.exp
index 0c8ce8c..9ac0142 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/cmse.exp
+++ b/gcc/testsuite/gcc.target/arm/cmse/cmse.exp
@@ -51,20 +51,37 @@ if {[check_effective_target_arm_arch_v8m_base_ok]} then {
 }
 
 if {[check_effective_target_arm_arch_v8m_main_ok]} then {
-    set MAINLINE_FLAGS [add_options_for_arm_arch_v8m_main ""]
-    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/*.c]] \
-	    "$MAINLINE_FLAGS" $DEFAULT_CFLAGS
+    set MAINLINE_8M_FLAGS [add_options_for_arm_arch_v8m_main ""]
+    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/8m/*.c]] \
+	    "$MAINLINE_8M_FLAGS" $DEFAULT_CFLAGS
     # Mainline -mfloat-abi=soft
-    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/soft/*.c]] \
-	    "$MAINLINE_FLAGS -mfloat-abi=soft" $DEFAULT_CFLAGS
-    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/softfp/*.c]] \
-	    "$MAINLINE_FLAGS" $DEFAULT_CFLAGS
-    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/softfp-sp/*.c]] \
-	    "$MAINLINE_FLAGS" $DEFAULT_CFLAGS
-    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/hard/*.c]] \
-	    "$MAINLINE_FLAGS" $DEFAULT_CFLAGS
-    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/hard-sp/*.c]] \
-	    "$MAINLINE_FLAGS" $DEFAULT_CFLAGS
+    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/8m/soft/*.c]] \
+	    "$MAINLINE_8M_FLAGS -mfloat-abi=soft" $DEFAULT_CFLAGS
+    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/8m/softfp/*.c]] \
+	    "$MAINLINE_8M_FLAGS" $DEFAULT_CFLAGS
+    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/8m/softfp-sp/*.c]] \
+	    "$MAINLINE_8M_FLAGS" $DEFAULT_CFLAGS
+    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/8m/hard/*.c]] \
+	    "$MAINLINE_8M_FLAGS" $DEFAULT_CFLAGS
+    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/8m/hard-sp/*.c]] \
+	    "$MAINLINE_8M_FLAGS" $DEFAULT_CFLAGS
+}
+
+if {[check_effective_target_arm_arch_v8_1m_main_ok]} then {
+    set MAINLINE_8_1M_FLAGS [add_options_for_arm_arch_v8_1m_main ""]
+    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/8_1m/*.c]] \
+	    "$MAINLINE_8_1M_FLAGS" $DEFAULT_CFLAGS
+    # Mainline -mfloat-abi=soft
+    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/8_1m/soft/*.c]] \
+	    "$MAINLINE_8_1M_FLAGS -mfloat-abi=soft" $DEFAULT_CFLAGS
+    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/8_1m/softfp/*.c]] \
+	    "$MAINLINE_8_1M_FLAGS" $DEFAULT_CFLAGS
+    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/8_1m/softfp-sp/*.c]] \
+	    "$MAINLINE_8_1M_FLAGS" $DEFAULT_CFLAGS
+    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/8_1m/hard/*.c]] \
+	    "$MAINLINE_8_1M_FLAGS" $DEFAULT_CFLAGS
+    gcc-dg-runtest [lsort [glob $srcdir/$subdir/mainline/8_1m/hard-sp/*.c]] \
+	    "$MAINLINE_8_1M_FLAGS" $DEFAULT_CFLAGS
 }
 
 set LTO_TORTURE_OPTIONS ${saved-lto_torture_options}
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-4.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c
index 55da2a0..62c63b8 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-4.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse" } */
 
-#include "../bitfield-4.x"
+#include "../../bitfield-4.x"
 
 /* { dg-final { scan-assembler "movw\tip, #65535" } } */
 /* { dg-final { scan-assembler "movt\tip, 255" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c
index 3833632..b718a70 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-5.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-5.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse" } */
 
-#include "../bitfield-5.x"
+#include "../../bitfield-5.x"
 
 /* { dg-final { scan-assembler "movw\tip, #8191" } } */
 /* { dg-final { scan-assembler "movt\tip, 255" } } */
@@ -13,4 +13,3 @@
 /* { dg-final { scan-assembler "mov\tr2, r4" } } */
 /* { dg-final { scan-assembler "mov\tr3, r4" } } */
 /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
-
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-6.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c
index 03c294e..16536ab 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-6.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse" } */
 
-#include "../bitfield-6.x"
+#include "../../bitfield-6.x"
 
 /* { dg-final { scan-assembler "movw\tip, #65535" } } */
 /* { dg-final { scan-assembler "movt\tip, 1023" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c
index 7692a69..0b3cc1e 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-7.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-7.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse" } */
 
-#include "../bitfield-7.x"
+#include "../../bitfield-7.x"
 
 /* { dg-final { scan-assembler "movw\tip, #8191" } } */
 /* { dg-final { scan-assembler "movt\tip, 255" } } */
@@ -13,4 +13,3 @@
 /* { dg-final { scan-assembler "mov\tr2, r4" } } */
 /* { dg-final { scan-assembler "mov\tr3, r4" } } */
 /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
-
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c
index a0a4887..914ea39 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-8.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse" } */
 
-#include "../bitfield-8.x"
+#include "../../bitfield-8.x"
 
 /* { dg-final { scan-assembler "mov\tip, #255" } } */
 /* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-9.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c
index 8bfeeb0..32435d2 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-9.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-9.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse" } */
 
-#include "../bitfield-9.x"
+#include "../../bitfield-9.x"
 
 /* { dg-final { scan-assembler "movw\tip, #1799" } } */
 /* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-and-union.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c
index aac5ae1a..68f9e22 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/bitfield-and-union.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse" } */
 
-#include "../bitfield-and-union.x"
+#include "../../bitfield-and-union.x"
 
 /* { dg-final { scan-assembler "movw\tip, #7939" } } */
 /* { dg-final { scan-assembler "movt\tip, 15" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c
index 70a0258..eb655b5 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-13.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c
@@ -1,9 +1,9 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
 /* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
 
-#include "../../cmse-13.x"
+#include "../../../cmse-13.x"
 
 /* Checks for saving and clearing prior to function call.  */
 /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
@@ -31,4 +31,3 @@
 
 /* Now we check that we use the correct intrinsic to call.  */
 /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
-
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c
new file mode 100644
index 0000000..ab266af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
+
+#include "../../../cmse-5.x"
+
+/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */
+/* { dg-final { scan-assembler "mov\tr0, lr" } } */
+/* { dg-final { scan-assembler "mov\tr1, lr" } } */
+/* { dg-final { scan-assembler "mov\tr2, lr" } } */
+/* { dg-final { scan-assembler "mov\tr3, lr" } } */
+/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts3, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts4, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts5, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts6, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts7, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts8, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts9, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts10, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts11, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts12, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */
+/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { ! arm_dsp } } } } */
+/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target arm_dsp } } } */
+/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */
+/* { dg-final { scan-assembler "bxns" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c
index 2c9dfcf..fd1a24b 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-7.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c
@@ -1,9 +1,9 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
 /* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
 
-#include "../../cmse-7.x"
+#include "../../../cmse-7.x"
 
 /* Checks for saving and clearing prior to function call.  */
 /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
@@ -31,4 +31,3 @@
 
 /* Now we check that we use the correct intrinsic to call.  */
 /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
-
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c
index b46585e..d8f9b77 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-8.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c
@@ -1,9 +1,9 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
 /* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
 
-#include "../../cmse-8.x"
+#include "../../../cmse-8.x"
 
 /* Checks for saving and clearing prior to function call.  */
 /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-13.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c
index 576013a..4878c6e 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-13.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c
@@ -1,9 +1,9 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
 /* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
 
-#include "../../cmse-13.x"
+#include "../../../cmse-13.x"
 
 /* Checks for saving and clearing prior to function call.  */
 /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c
new file mode 100644
index 0000000..82aad2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
+
+#include "../../../cmse-5.x"
+
+/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */
+/* { dg-final { scan-assembler "mov\tr0, lr" } } */
+/* { dg-final { scan-assembler "mov\tr1, lr" } } */
+/* { dg-final { scan-assembler "mov\tr2, lr" } } */
+/* { dg-final { scan-assembler "mov\tr3, lr" } } */
+/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td3, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td4, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */
+/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { ! arm_dsp } } } } */
+/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target arm_dsp } } } */
+/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */
+/* { dg-final { scan-assembler "bxns" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c
index 3e502a2..8e054c2 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-7.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c
@@ -1,9 +1,9 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
 /* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
 
-#include "../../cmse-7.x"
+#include "../../../cmse-7.x"
 
 /* Checks for saving and clearing prior to function call.  */
 /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
@@ -23,4 +23,3 @@
 
 /* Now we check that we use the correct intrinsic to call.  */
 /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
-
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c
index 5ed3e7a3..e74cea7 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-8.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c
@@ -1,9 +1,9 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
 /* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
 
-#include "../../cmse-8.x"
+#include "../../../cmse-8.x"
 
 /* Checks for saving and clearing prior to function call.  */
 /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-13.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c
index 778801f..4c4a0c9 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-13.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-13.c
@@ -1,8 +1,8 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=soft" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=hard" -mfloat-abi=softfp } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */
 
-#include "../../cmse-13.x"
+#include "../../../cmse-13.x"
 
 /* Checks for saving and clearing prior to function call.  */
 /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
@@ -16,4 +16,3 @@
 
 /* Now we check that we use the correct intrinsic to call.  */
 /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
-
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c
new file mode 100644
index 0000000..c684d79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=soft" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */
+
+#include "../../../cmse-5.x"
+
+/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */
+/* { dg-final { scan-assembler "mov\tr1, lr" } } */
+/* { dg-final { scan-assembler "mov\tr2, lr" } } */
+/* { dg-final { scan-assembler "mov\tr3, lr" } } */
+/* { dg-final { scan-assembler "mov\tip, lr" } } */
+/* { dg-final { scan-assembler-not "vmov" } } */
+/* { dg-final { scan-assembler-not "vmsr" } } */
+/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { ! arm_dsp } } } } */
+/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target arm_dsp } } } */
+/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */
+/* { dg-final { scan-assembler "bxns" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c
index 5c9539f..4cb6a54 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-7.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-7.c
@@ -1,8 +1,8 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=soft" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=hard" -mfloat-abi=softfp } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */
 
-#include "../../cmse-7.x"
+#include "../../../cmse-7.x"
 
 /* Checks for saving and clearing prior to function call.  */
 /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
@@ -16,4 +16,3 @@
 
 /* Now we check that we use the correct intrinsic to call.  */
 /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
-
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c
index 0947c9b..4764b2f 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-8.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/soft/cmse-8.c
@@ -1,8 +1,8 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=soft" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=hard" -mfloat-abi=softfp } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */
 
-#include "../../cmse-8.x"
+#include "../../../cmse-8.x"
 
 /* Checks for saving and clearing prior to function call.  */
 /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c
new file mode 100644
index 0000000..9b2e756
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */
+/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
+
+#include "../../../cmse-5.x"
+
+/* { dg-final { scan-assembler "__acle_se_foo:" } } */
+/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */
+/* { dg-final { scan-assembler-not "mov\tr0, lr" } } */
+/* { dg-final { scan-assembler "mov\tr1, lr" } } */
+/* { dg-final { scan-assembler "mov\tr2, lr" } } */
+/* { dg-final { scan-assembler "mov\tr3, lr" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts0, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts3, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts4, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts5, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts6, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts7, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts8, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts9, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts10, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts11, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts12, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */
+/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { ! arm_dsp } } } } */
+/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target arm_dsp } } } */
+/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */
+/* { dg-final { scan-assembler "bxns" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c
index 792d444..9e93d75 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-7.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-7.c
@@ -1,9 +1,9 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */
 /* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
 
-#include "../../cmse-7.x"
+#include "../../../cmse-7.x"
 
 /* Checks for saving and clearing prior to function call.  */
 /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
@@ -15,4 +15,3 @@
 
 /* Now we check that we use the correct intrinsic to call.  */
 /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
-
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c
index 2d9797b..566889e 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-8.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-8.c
@@ -1,9 +1,9 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */
 /* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
 
-#include "../../cmse-8.x"
+#include "../../../cmse-8.x"
 
 /* Checks for saving and clearing prior to function call.  */
 /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-13.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c
index 56b88f89..0ee28de 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-13.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-13.c
@@ -1,9 +1,9 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */
 /* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
 
-#include "../../cmse-13.x"
+#include "../../../cmse-13.x"
 
 /* Checks for saving and clearing prior to function call.  */
 /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
@@ -14,4 +14,3 @@
 
 /* Now we check that we use the correct intrinsic to call.  */
 /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
-
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c
new file mode 100644
index 0000000..5af1fdb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */
+/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
+
+#include "../../../cmse-5.x"
+
+/* { dg-final { scan-assembler "__acle_se_foo:" } } */
+/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */
+/* { dg-final { scan-assembler-not "mov\tr0, lr" } } */
+/* { dg-final { scan-assembler "mov\tr1, lr" } } */
+/* { dg-final { scan-assembler "mov\tr2, lr" } } */
+/* { dg-final { scan-assembler "mov\tr3, lr" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td0, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td3, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td4, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */
+/* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { ! arm_dsp } } } } */
+/* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target arm_dsp } } } */
+/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */
+/* { dg-final { scan-assembler "bxns" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c
index 45be75f..1c38290 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-7.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-7.c
@@ -1,9 +1,9 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */
 /* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
 
-#include "../../cmse-7.x"
+#include "../../../cmse-7.x"
 
 /* Checks for saving and clearing prior to function call.  */
 /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
@@ -15,4 +15,3 @@
 
 /* Now we check that we use the correct intrinsic to call.  */
 /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
-
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c
index f98e9db..39c2e72 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-8.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-8.c
@@ -1,9 +1,9 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */
 /* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
 
-#include "../../cmse-8.x"
+#include "../../../cmse-8.x"
 
 /* Checks for saving and clearing prior to function call.  */
 /* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/union-1.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-1.c
index 071955f..d51db02 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/union-1.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-1.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse" } */
 
-#include "../union-1.x"
+#include "../../union-1.x"
 
 /* { dg-final { scan-assembler "movw\tip, #8063" } } */
 /* { dg-final { scan-assembler "movt\tip, 63" } } */
@@ -13,4 +13,3 @@
 /* { dg-final { scan-assembler "mov\tr2, r4" } } */
 /* { dg-final { scan-assembler "mov\tr3, r4" } } */
 /* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
-
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/union-2.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-2.c
index c743193..131afbb 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/union-2.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-2.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse" } */
 
-#include "../union-2.x"
+#include "../../union-2.x"
 
 /* { dg-final { scan-assembler "movw\tip, #8191" } } */
 /* { dg-final { scan-assembler "movt\tip, 63" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-4.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-4.c
new file mode 100644
index 0000000..62c63b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-4.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse" } */
+
+#include "../../bitfield-4.x"
+
+/* { dg-final { scan-assembler "movw\tip, #65535" } } */
+/* { dg-final { scan-assembler "movt\tip, 255" } } */
+/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
+/* { dg-final { scan-assembler "mov\tip, #255" } } */
+/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
+/* { dg-final { scan-assembler "mov\tip, #3" } } */
+/* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-5.c
new file mode 100644
index 0000000..b718a70
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-5.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse" } */
+
+#include "../../bitfield-5.x"
+
+/* { dg-final { scan-assembler "movw\tip, #8191" } } */
+/* { dg-final { scan-assembler "movt\tip, 255" } } */
+/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
+/* { dg-final { scan-assembler "movw\tip, #2047" } } */
+/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "mov\tr2, r4" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-6.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-6.c
new file mode 100644
index 0000000..16536ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-6.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse" } */
+
+#include "../../bitfield-6.x"
+
+/* { dg-final { scan-assembler "movw\tip, #65535" } } */
+/* { dg-final { scan-assembler "movt\tip, 1023" } } */
+/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
+/* { dg-final { scan-assembler "mov\tip, #3" } } */
+/* { dg-final { scan-assembler "movt\tip, 32767" } } */
+/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
+/* { dg-final { scan-assembler "mov\tip, #255" } } */
+/* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-7.c
new file mode 100644
index 0000000..0b3cc1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-7.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse" } */
+
+#include "../../bitfield-7.x"
+
+/* { dg-final { scan-assembler "movw\tip, #8191" } } */
+/* { dg-final { scan-assembler "movt\tip, 255" } } */
+/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
+/* { dg-final { scan-assembler "movw\tip, #2047" } } */
+/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "mov\tr2, r4" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-8.c
new file mode 100644
index 0000000..914ea39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-8.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse" } */
+
+#include "../../bitfield-8.x"
+
+/* { dg-final { scan-assembler "mov\tip, #255" } } */
+/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
+/* { dg-final { scan-assembler "mov\tip, #1" } } */
+/* { dg-final { scan-assembler "movt\tip, 65535" } } */
+/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
+/* { dg-final { scan-assembler "movw\tip, #65535" } } */
+/* { dg-final { scan-assembler "movt\tip, 31" } } */
+/* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-9.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-9.c
new file mode 100644
index 0000000..32435d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-9.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse" } */
+
+#include "../../bitfield-9.x"
+
+/* { dg-final { scan-assembler "movw\tip, #1799" } } */
+/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "mov\tr1, r4" } } */
+/* { dg-final { scan-assembler "mov\tr2, r4" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-and-union.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-and-union.c
new file mode 100644
index 0000000..68f9e22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/bitfield-and-union.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse" } */
+
+#include "../../bitfield-and-union.x"
+
+/* { dg-final { scan-assembler "movw\tip, #7939" } } */
+/* { dg-final { scan-assembler "movt\tip, 15" } } */
+/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
+/* { dg-final { scan-assembler "movw\tip, #65535" } } */
+/* { dg-final { scan-assembler "movt\tip, 2047" } } */
+/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
+/* { dg-final { scan-assembler "mov\tip, #1" } } */
+/* { dg-final { scan-assembler "movt\tip, 65535" } } */
+/* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
+/* { dg-final { scan-assembler "movw\tip, #65535" } } */
+/* { dg-final { scan-assembler "movt\tip, 31" } } */
+/* { dg-final { scan-assembler "and\tr3, r3, ip" } } */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-13.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-13.c
new file mode 100644
index 0000000..eb655b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-13.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
+
+#include "../../../cmse-13.x"
+
+/* Checks for saving and clearing prior to function call.  */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "mov\tr0, r4" } } */
+/* { dg-final { scan-assembler "mov\tr1, r4" } } */
+/* { dg-final { scan-assembler "mov\tr2, r4" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
+/* { dg-final { scan-assembler-not "vmov\.f32\ts2, #1\.0" } } */
+/* { dg-final { scan-assembler-not "vmov\.f32\ts3, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts4, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts5, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts6, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts7, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts8, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts9, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts10, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts11, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts12, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */
+
+/* Now we check that we use the correct intrinsic to call.  */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-5.c
index e946276..3b73c0e 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-5.c
@@ -1,9 +1,9 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
 /* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
 
-#include "../../cmse-5.x"
+#include "../../../cmse-5.x"
 
 /* { dg-final { scan-assembler "mov\tr0, lr" } } */
 /* { dg-final { scan-assembler "mov\tr1, lr" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-7.c
new file mode 100644
index 0000000..fd1a24b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-7.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
+
+#include "../../../cmse-7.x"
+
+/* Checks for saving and clearing prior to function call.  */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "mov\tr0, r4" } } */
+/* { dg-final { scan-assembler "mov\tr1, r4" } } */
+/* { dg-final { scan-assembler "mov\tr2, r4" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts0, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts3, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts4, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts5, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts6, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts7, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts8, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts9, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts10, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts11, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts12, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */
+
+/* Now we check that we use the correct intrinsic to call.  */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-8.c
new file mode 100644
index 0000000..d8f9b77
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-8.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-sp-d16" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
+
+#include "../../../cmse-8.x"
+
+/* Checks for saving and clearing prior to function call.  */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "mov\tr0, r4" } } */
+/* { dg-final { scan-assembler "mov\tr1, r4" } } */
+/* { dg-final { scan-assembler "mov\tr2, r4" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */
+/* { dg-final { scan-assembler-not "vmov\.f32\ts1, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts3, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts4, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts5, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts6, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts7, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts8, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts9, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts10, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts11, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts12, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */
+
+/* Now we check that we use the correct intrinsic to call.  */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard/cmse-13.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard/cmse-13.c
new file mode 100644
index 0000000..4878c6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard/cmse-13.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
+
+#include "../../../cmse-13.x"
+
+/* Checks for saving and clearing prior to function call.  */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "mov\tr0, r4" } } */
+/* { dg-final { scan-assembler "mov\tr1, r4" } } */
+/* { dg-final { scan-assembler "mov\tr2, r4" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
+/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */
+/* { dg-final { scan-assembler-not "vmov\.f64\td0, #1\.0" } } */
+/* { dg-final { scan-assembler-not "vmov\.f64\td1, #1\.0" } } */
+/* { dg-final { scan-assembler-not "vmov\.f32\ts2, #1\.0" } } */
+/* { dg-final { scan-assembler-not "vmov\.f32\ts3, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td3, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td4, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */
+
+/* Now we check that we use the correct intrinsic to call.  */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard/cmse-5.c
index 863b412..d6e758c 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/hard/cmse-5.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard/cmse-5.c
@@ -1,9 +1,9 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=softfp } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
 /* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
 
-#include "../../cmse-5.x"
+#include "../../../cmse-5.x"
 
 /* { dg-final { scan-assembler "mov\tr0, lr" } } */
 /* { dg-final { scan-assembler "mov\tr1, lr" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard/cmse-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard/cmse-7.c
new file mode 100644
index 0000000..8e054c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard/cmse-7.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
+
+#include "../../../cmse-7.x"
+
+/* Checks for saving and clearing prior to function call.  */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "mov\tr0, r4" } } */
+/* { dg-final { scan-assembler "mov\tr1, r4" } } */
+/* { dg-final { scan-assembler "mov\tr2, r4" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td0, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td3, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td4, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */
+
+/* Now we check that we use the correct intrinsic to call.  */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard/cmse-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard/cmse-8.c
new file mode 100644
index 0000000..e74cea7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/hard/cmse-8.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=hard -mfpu=fpv5-d16" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
+
+#include "../../../cmse-8.x"
+
+/* Checks for saving and clearing prior to function call.  */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "mov\tr0, r4" } } */
+/* { dg-final { scan-assembler "mov\tr1, r4" } } */
+/* { dg-final { scan-assembler "mov\tr2, r4" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+/* { dg-final { scan-assembler-not "vmov\.f64\td0, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td3, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td4, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */
+/* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */
+
+/* Now we check that we use the correct intrinsic to call.  */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/soft/cmse-13.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/soft/cmse-13.c
new file mode 100644
index 0000000..4c4a0c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/soft/cmse-13.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=soft" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */
+
+#include "../../../cmse-13.x"
+
+/* Checks for saving and clearing prior to function call.  */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */
+/* { dg-final { scan-assembler "mov\tr1, r4" } } */
+/* { dg-final { scan-assembler-not "mov\tr2, r4" } } */
+/* { dg-final { scan-assembler-not "mov\tr3, r4" } } */
+/* { dg-final { scan-assembler-not "vmov" } } */
+/* { dg-final { scan-assembler-not "vmsr" } } */
+
+/* Now we check that we use the correct intrinsic to call.  */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/soft/cmse-5.c
index 6c326ed..71971b0 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/soft/cmse-5.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/soft/cmse-5.c
@@ -1,8 +1,8 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=soft" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=hard" -mfloat-abi=softfp } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */
 
-#include "../../cmse-5.x"
+#include "../../../cmse-5.x"
 
 /* { dg-final { scan-assembler "mov\tr1, lr" } } */
 /* { dg-final { scan-assembler "mov\tr2, lr" } } */
@@ -13,4 +13,3 @@
 /* { dg-final { scan-assembler "msr\tAPSR_nzcvq, lr" { target { ! arm_dsp } } } } */
 /* { dg-final { scan-assembler "msr\tAPSR_nzcvqg, lr" { target arm_dsp } } } */
 /* { dg-final { scan-assembler "bxns" } } */
-
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/soft/cmse-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/soft/cmse-7.c
new file mode 100644
index 0000000..4cb6a54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/soft/cmse-7.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=soft" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */
+
+#include "../../../cmse-7.x"
+
+/* Checks for saving and clearing prior to function call.  */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "mov\tr0, r4" } } */
+/* { dg-final { scan-assembler "mov\tr1, r4" } } */
+/* { dg-final { scan-assembler "mov\tr2, r4" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+/* { dg-final { scan-assembler-not "vmov" } } */
+/* { dg-final { scan-assembler-not "vmsr" } } */
+
+/* Now we check that we use the correct intrinsic to call.  */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/soft/cmse-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/soft/cmse-8.c
new file mode 100644
index 0000000..4764b2f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/soft/cmse-8.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=soft" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */
+
+#include "../../../cmse-8.x"
+
+/* Checks for saving and clearing prior to function call.  */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */
+/* { dg-final { scan-assembler-not "mov\tr1, r4" } } */
+/* { dg-final { scan-assembler "mov\tr2, r4" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+/* { dg-final { scan-assembler-not "vmov" } } */
+/* { dg-final { scan-assembler-not "vmsr" } } */
+
+/* Now we check that we use the correct intrinsic to call.  */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-5.c
index 9f5466d..f550b77 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-5.c
@@ -1,9 +1,9 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */
 /* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
 
-#include "../../cmse-5.x"
+#include "../../../cmse-5.x"
 
 /* { dg-final { scan-assembler "__acle_se_foo:" } } */
 /* { dg-final { scan-assembler-not "mov\tr0, lr" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-7.c
new file mode 100644
index 0000000..9e93d75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-7.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */
+/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
+
+#include "../../../cmse-7.x"
+
+/* Checks for saving and clearing prior to function call.  */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "mov\tr0, r4" } } */
+/* { dg-final { scan-assembler "mov\tr1, r4" } } */
+/* { dg-final { scan-assembler "mov\tr2, r4" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+
+/* Now we check that we use the correct intrinsic to call.  */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-8.c
new file mode 100644
index 0000000..566889e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-8.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-sp-d16" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */
+/* { dg-skip-if "Skip these if testing double precision" {*-*-*} {"-mfpu=fpv[4-5]-d16"} {""} } */
+
+#include "../../../cmse-8.x"
+
+/* Checks for saving and clearing prior to function call.  */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */
+/* { dg-final { scan-assembler-not "mov\tr1, r4" } } */
+/* { dg-final { scan-assembler "mov\tr2, r4" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+
+/* Now we check that we use the correct intrinsic to call.  */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-13.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-13.c
new file mode 100644
index 0000000..0ee28de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-13.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */
+/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
+
+#include "../../../cmse-13.x"
+
+/* Checks for saving and clearing prior to function call.  */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */
+/* { dg-final { scan-assembler "\n\tmov\tr1, r4" } } */
+/* { dg-final { scan-assembler-not "\n\tmov\tr2, r4\n\tmov\tr3, r4" } } */
+
+/* Now we check that we use the correct intrinsic to call.  */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-5.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-5.c
index 7aa35f0..cf8f3ab 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/mainline/softfp/cmse-5.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-5.c
@@ -1,9 +1,9 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" }  */
-/* { dg-skip-if "Do not combine float-abi= hard | soft | softfp" {*-*-*} {"-mfloat-abi=soft" -mfloat-abi=hard } {""} } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */
 /* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
 
-#include "../../cmse-5.x"
+#include "../../../cmse-5.x"
 
 /* { dg-final { scan-assembler "__acle_se_foo:" } } */
 /* { dg-final { scan-assembler-not "mov\tr0, lr" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-7.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-7.c
new file mode 100644
index 0000000..1c38290
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-7.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */
+/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
+
+#include "../../../cmse-7.x"
+
+/* Checks for saving and clearing prior to function call.  */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "mov\tr0, r4" } } */
+/* { dg-final { scan-assembler "mov\tr1, r4" } } */
+/* { dg-final { scan-assembler "mov\tr2, r4" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+
+/* Now we check that we use the correct intrinsic to call.  */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-8.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-8.c
new file mode 100644
index 0000000..39c2e72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/softfp/cmse-8.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" }  */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */
+/* { dg-skip-if "Skip these if testing single precision" {*-*-*} {"-mfpu=*-sp-*"} {""} } */
+
+#include "../../../cmse-8.x"
+
+/* Checks for saving and clearing prior to function call.  */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler-not "mov\tr0, r4" } } */
+/* { dg-final { scan-assembler-not "mov\tr1, r4" } } */
+/* { dg-final { scan-assembler "mov\tr2, r4" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+
+/* Now we check that we use the correct intrinsic to call.  */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/union-1.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/union-1.c
new file mode 100644
index 0000000..d51db02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/union-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse" } */
+
+#include "../../union-1.x"
+
+/* { dg-final { scan-assembler "movw\tip, #8063" } } */
+/* { dg-final { scan-assembler "movt\tip, 63" } } */
+/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
+/* { dg-final { scan-assembler "movw\tip, #511" } } */
+/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "mov\tr2, r4" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/union-2.c b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/union-2.c
new file mode 100644
index 0000000..131afbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/cmse/mainline/8m/union-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mcmse" } */
+
+#include "../../union-2.x"
+
+/* { dg-final { scan-assembler "movw\tip, #8191" } } */
+/* { dg-final { scan-assembler "movt\tip, 63" } } */
+/* { dg-final { scan-assembler "and\tr0, r0, ip" } } */
+/* { dg-final { scan-assembler "movw\tip, #511" } } */
+/* { dg-final { scan-assembler "movt\tip, 65535" } } */
+/* { dg-final { scan-assembler "and\tr1, r1, ip" } } */
+/* { dg-final { scan-assembler "movw\tip, #65535" } } */
+/* { dg-final { scan-assembler "movt\tip, 31" } } */
+/* { dg-final { scan-assembler "and\tr2, r2, ip" } } */
+/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
+/* { dg-final { scan-assembler "mov\tr3, r4" } } */
+/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
diff --git a/gcc/testsuite/gcc.target/arm/cmse/struct-1.c b/gcc/testsuite/gcc.target/arm/cmse/struct-1.c
index 874da3c..5f6891a 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/struct-1.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/struct-1.c
@@ -25,9 +25,9 @@ main (void)
   return 0;
 }
 
+/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" { target arm_cmse_clear_ok } } } */
 /* { dg-final { scan-assembler "movs\tr1, #255" } } */
 /* { dg-final { scan-assembler "movt\tr1, 65535" } } */
 /* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */
+/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" { target arm_cmse_clear_ok } } } */
 /* { dg-final { scan-assembler "bxns" } } */
-
-
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index b247d94..7916698 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4525,6 +4525,19 @@ proc check_effective_target_arm_cmse_ok {} {
     } "-mcmse"];
 }
 
+# Return 1 if this is an ARM target where ARMv8-M Security Extensions with
+# clearing instructions (clrm, vscclrm, vstr/vldr with FPCXT) is available.
+
+proc check_effective_target_arm_cmse_clear_ok {} {
+    return [check_no_compiler_messages arm_cmse_clear object {
+	int
+	foo (void)
+	{
+	  asm ("clrm {r1, r2}");
+	}
+    } "-mcmse"];
+}
+
 # Return 1 if this compilation turns on string_ops_prefer_neon on.
 
 proc check_effective_target_arm_tune_string_ops_prefer_neon { } {
author	Mihail Ionescu <mihail.ionescu@arm.com>	2020-01-15 10:33:52 +0000
committer	Mihail Ionescu <mihail.ionescu@arm.com>	2020-01-16 15:11:15 +0000
commit	e0e4be48a9892195f11d1b608793c3a30b640f54 (patch)
tree	c76fd00b5769275e5ef1d80ce7f812d711acf098 /gcc
parent	e27cf2e372651997c3b46a5662dd4d47c53dd13b (diff)
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