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| author | Uros Bizjak <ubizjak@gmail.com> | 2008-11-25 01:12:15 +0100 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2008-11-25 01:12:15 +0100 |
| commit | decc2ec39ac3c4ffc7ba25e2c6a52a4d4bad62fa (patch) | |
| tree | 8e07a39330d1ebe644c0770206cc9d3a6ccc8002 /gcc | |
| parent | 467a1bf1e95118b02793c3eef6422e8744245c11 (diff) | |
| download | gcc-decc2ec39ac3c4ffc7ba25e2c6a52a4d4bad62fa.zip gcc-decc2ec39ac3c4ffc7ba25e2c6a52a4d4bad62fa.tar.gz gcc-decc2ec39ac3c4ffc7ba25e2c6a52a4d4bad62fa.tar.bz2 | |
re PR c++/38256 (ICE with "operator auto")
PR target/38256
* config/i386/sync.md (memory_barrier_nosse): New insn
(memory_barrier): Generate memory_barrier_nosse insn for !TARGET_SSE2.
From-SVN: r142177
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/sync.md | 25 |
2 files changed, 24 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9dd40f7..b90d1f9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2008-11-25 Uros Bizjak <ubizjak@gmail.com> + + PR target/38256 + * config/i386/sync.md (memory_barrier_nosse): New insn + (memory_barrier): Generate memory_barrier_nosse insn for !TARGET_SSE2. + 2008-11-24 Maxim Kuvyrkov <maxim@codesourcery.com> * config/m68k/m68k.md (cmpdi): Use (scratch) instead of pseudo. diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md index e090ea7..8aad0c4 100644 --- a/gcc/config/i386/sync.md +++ b/gcc/config/i386/sync.md @@ -36,19 +36,30 @@ (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))] "" { + operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); + MEM_VOLATILE_P (operands[0]) = 1; + if (!TARGET_SSE2) { - /* Emit a locked no-operation when SSE2 is not available. */ - int slot = virtuals_instantiated ? SLOT_TEMP : SLOT_VIRTUAL; - rtx temp = assign_386_stack_local (QImode, slot); - emit_insn (gen_sync_iorqi (temp, CONST0_RTX (QImode))); + emit_insn (gen_memory_barrier_nosse (operands[0])); DONE; } - - operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); - MEM_VOLATILE_P (operands[0]) = 1; }) +(define_insn "memory_barrier_nosse" + [(set (match_operand:BLK 0 "" "") + (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE)) + (clobber (reg:CC FLAGS_REG))] + + "!TARGET_SSE2" +{ + if (TARGET_64BIT) + return "lock{%;| }or{q}\t{$0, (%%rsp)|QWORD PTR [rsp], 0}"; + else + return "lock{%;| }or{l}\t{$0, (%%esp)|DWORD PTR [esp], 0}"; +} + [(set_attr "memory" "unknown")]) + ;; ??? It would be possible to use cmpxchg8b on pentium for DImode ;; changes. It's complicated because the insn uses ecx:ebx as the ;; new value; note that the registers are reversed from the order |