diff options
| author | Richard Sandiford <rdsandiford@googlemail.com> | 2012-10-02 19:37:24 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2012-10-02 19:37:24 +0000 |
| commit | dccb154f149a2d99eb06fed4e2a32479f2d5174c (patch) | |
| tree | 006a6a311c4126c6c3dc243bf12a94cf5463cc1b /gcc | |
| parent | a2c19e9343706412d3320e3b6b2688d01ace96a5 (diff) | |
| download | gcc-dccb154f149a2d99eb06fed4e2a32479f2d5174c.zip gcc-dccb154f149a2d99eb06fed4e2a32479f2d5174c.tar.gz gcc-dccb154f149a2d99eb06fed4e2a32479f2d5174c.tar.bz2 | |
mips.md (*baddu_si_eb, [...]): Merge into...
gcc/
* config/mips/mips.md (*baddu_si_eb, *baddu_si_el): Merge into...
(*baddu_si): ...this new pattern.
From-SVN: r191997
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 19 |
2 files changed, 9 insertions, 15 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2bdf661..46cdf7d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2012-10-02 Richard Sandiford <rdsandiford@googlemail.com> + * config/mips/mips.md (*baddu_si_eb, *baddu_si_el): Merge into... + (*baddu_si): ...this new pattern. + +2012-10-02 Richard Sandiford <rdsandiford@googlemail.com> + * ira-int.h (target_ira_int): Add x_ira_useful_class_mode_regs. (ira_useful_class_mode_regs): New macro. * ira.c (clarify_prohibited_class_mode_regs): Set up diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 86d2c55..787852c 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -1293,23 +1293,12 @@ ;; Combiner patterns for unsigned byte-add. -(define_insn "*baddu_si_eb" +(define_insn "*baddu_si" [(set (match_operand:SI 0 "register_operand" "=d") (zero_extend:SI - (subreg:QI - (plus:SI (match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d")) 3)))] - "ISA_HAS_BADDU && BYTES_BIG_ENDIAN" - "baddu\\t%0,%1,%2" - [(set_attr "alu_type" "add")]) - -(define_insn "*baddu_si_el" - [(set (match_operand:SI 0 "register_operand" "=d") - (zero_extend:SI - (subreg:QI - (plus:SI (match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d")) 0)))] - "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN" + (plus:QI (match_operand:QI 1 "register_operand" "d") + (match_operand:QI 2 "register_operand" "d"))))] + "ISA_HAS_BADDU" "baddu\\t%0,%1,%2" [(set_attr "alu_type" "add")]) |