Daily bump.

4 files changed, 133 insertions, 1 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index aa86b71..b0365c1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,60 @@
+2025-02-18  Andi Kleen  <ak@gcc.gnu.org>
+
+	* doc/invoke.texi:
+
+2025-02-18  David Malcolm  <dmalcolm@redhat.com>
+
+	* opts-diagnostic.cc (sarif_scheme_handler::make_sink): Put
+	properties in alphabetical order.
+
+2025-02-18  Robin Dapp  <rdapp@ventanamicro.com>
+
+	PR target/115703
+	* config/riscv/riscv-vsetvl.cc: Use max_sew for calculating the
+	new LMUL.
+
+2025-02-18  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR rtl-optimization/108840
+	* late-combine.cc (late_combine::check_register_pressure):
+	Take only allocatable registers into account when checking
+	the permissiveness of register classes.
+
+2025-02-18  Alex Coplan  <alex.coplan@arm.com>
+
+	PR rtl-optimization/118320
+	* pair-fusion.cc (pair_fusion_bb_info::fuse_pair): Tweak wording in dump
+	message when punting on invalid use arrays.
+
+2025-02-18  Soumya AR  <soumyaa@nvidia.com>
+
+	* config/aarch64/tuning_models/generic_armv8_a.h: Updated prefetch
+	struct pointer.
+
+2025-02-18  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/98845
+	* tree-ssa-tail-merge.cc (stmt_local_def): Consider a
+	def with no uses not local.
+
+2025-02-18  Pan Li  <pan2.li@intel.com>
+
+	PR target/118540
+	* config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
+	Report error when cmd xlen is different with target attribute.
+
+2025-02-18  Haochen Jiang  <haochen.jiang@intel.com>
+
+	* config/i386/i386.opt.urls: Adjust the order for avx10.2
+	and avx10.2-512 due to their order change in i386.opt.
+
+2025-02-18  Alexandre Oliva  <oliva@adacore.com>
+
+	PR tree-optimization/118805
+	* gimple-fold.cc (fold_truth_andor_for_combine): Detect and
+	cope with zero-extension in signbit tests.  Reject swapping
+	right-compare operands if rsignbit.
+
 2025-02-17  Uros Bizjak  <ubizjak@gmail.com>
 
 	* config/i386/i386.cc (ix86_find_all_reg_use):
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index bec432b..7462e91 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250218
+20250219
diff --git a/gcc/analyzer/ChangeLog b/gcc/analyzer/ChangeLog
index 9fd3052..69955f7 100644
--- a/gcc/analyzer/ChangeLog
+++ b/gcc/analyzer/ChangeLog
@@ -1,3 +1,13 @@
+2025-02-18  David Malcolm  <dmalcolm@redhat.com>
+
+	* diagnostic-manager.cc
+	(saved_diagnostic::maybe_add_sarif_properties): Add various
+	properties for debugging, for m_stmt, m_var, and m_duplicates.
+	Remove stray 'if' statement.  Capture the kind of the
+	pending_diagnostic.
+	* region-model.cc
+	(poisoned_value_diagnostic::maybe_add_sarif_properties): New.
+
 2024-12-06  David Malcolm  <dmalcolm@redhat.com>
 
 	* region-model.cc: Include "gcc-urlifier.h".
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ee2632a..0d836d5 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,68 @@
+2025-02-18  Robin Dapp  <rdapp@ventanamicro.com>
+
+	PR target/115703
+	* gcc.target/riscv/rvv/autovec/pr115703-run.c: New test.
+	* gcc.target/riscv/rvv/autovec/pr115703.c: New test.
+
+2025-02-18  John David Anglin  <danglin@gcc.gnu.org>
+
+	PR testsuite/116986
+	* gcc.dg/crc-builtin-rev-target32.c: Include stdint.h
+	instead of stdint-gcc.h.
+	* gcc.dg/crc-builtin-rev-target64.c: Likewise.
+	* gcc.dg/crc-builtin-target32.c: Likewise.
+	* gcc.dg/crc-builtin-target64.c: Likewise.
+	* gcc.dg/torture/pr115387-2.c: Likewise.
+
+2025-02-18  Tobias Burnus  <tburnus@baylibre.com>
+
+	* gfortran.dg/gomp/metadirective-3.f90: Add xfail when
+	compiling for offload_nvptx.
+
+2025-02-18  Richard Sandiford  <richard.sandiford@arm.com>
+
+	PR rtl-optimization/108840
+	* gcc.target/aarch64/pr108840.c: Run at -O2 but disable combine.
+
+2025-02-18  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/98845
+	* gcc.dg/pr98845.c: New testcase.
+	* gcc.dg/pr81192.c: Adjust.
+
+2025-02-18  Jin Ma  <jinma@linux.alibaba.com>
+
+	* gcc.target/riscv/rvv/base/bug-9.c: Added new failure check.
+	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c: Likewise.
+	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c: Likewise.
+	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c: Likewise.
+	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c: Likewise.
+	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c: Likewise.
+	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c: Likewise.
+	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c: Likewise.
+	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c: Likewise.
+	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c: Likewise.
+	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c: Likewise.
+	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c: Likewise.
+	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c: Likewise.
+	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c: Likewise.
+	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c: Likewise.
+
+2025-02-18  Pan Li  <pan2.li@intel.com>
+
+	PR target/118540
+	* gcc.target/riscv/rvv/base/pr118540-1.c: New test.
+	* gcc.target/riscv/rvv/base/pr118540-2.c: New test.
+
+2025-02-18  Alexandre Oliva  <oliva@adacore.com>
+
+	* lib/scanasm.exp (check-function-bodies): Fix usage comment.
+
+2025-02-18  Alexandre Oliva  <oliva@adacore.com>
+
+	PR tree-optimization/118805
+	* gcc.dg/field-merge-26.c: New.
+
 2025-02-17  Tobias Burnus  <tburnus@baylibre.com>
 
 	PR fortran/115271