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authorPaolo Bonzini <bonzini@gnu.org>2004-03-05 10:41:27 +0000
committerPaolo Bonzini <bonzini@gcc.gnu.org>2004-03-05 10:41:27 +0000
commitd2782048a2d28004bbb2fca8aad5ced64774b638 (patch)
tree84242829927d10321448fbb1078ced9276267afc /gcc
parentf894b69b7561a8be2b2def5ae0adad4d2e2e5ec5 (diff)
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simplify-rtx.c (simplify_relational_operation): If flag_wrapv is set...
2004-03-05 Paolo Bonzini <bonzini@gnu.org> * simplify-rtx.c (simplify_relational_operation): If flag_wrapv is set, do not move terms between the two side of a relational operator. From-SVN: r78962
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog6
-rw-r--r--gcc/simplify-rtx.c5
2 files changed, 9 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0023618..723492a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,11 @@
2004-03-05 Paolo Bonzini <bonzini@gnu.org>
+ * simplify-rtx.c (simplify_relational_operation): If
+ flag_wrapv is set, do not move terms between the two
+ side of a relational operator.
+
+2004-03-05 Paolo Bonzini <bonzini@gnu.org>
+
* rtlanal.c: Include target.h and output.h
(rtx_cost, address_cost, default_address_cost): Move from...
* cse.c (rtx_cost, address_cost, default_address_cost):
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index bae37f8..b86a8b2 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -2559,9 +2559,10 @@ simplify_relational_operation (enum rtx_code code, enum machine_mode mode,
If CODE is an unsigned comparison, then we can never do this optimization,
because it gives an incorrect result if the subtraction wraps around zero.
ANSI C defines unsigned operations such that they never overflow, and
- thus such cases can not be ignored. */
+ thus such cases can not be ignored; but we cannot do it even for
+ signed comparisons for languages such as Java, so test flag_wrapv. */
- if (INTEGRAL_MODE_P (mode) && trueop1 != const0_rtx
+ if (!flag_wrapv && INTEGRAL_MODE_P (mode) && trueop1 != const0_rtx
&& ! ((GET_CODE (op0) == REG || GET_CODE (trueop0) == CONST_INT)
&& (GET_CODE (op1) == REG || GET_CODE (trueop1) == CONST_INT))
&& 0 != (tem = simplify_binary_operation (MINUS, mode, op0, op1))