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| author | Peter Barada <peter@the-baradas.com> | 2004-05-29 15:10:41 +0000 |
|---|---|---|
| committer | Bernardo Innocenti <bernie@gcc.gnu.org> | 2004-05-29 17:10:41 +0200 |
| commit | d1fe6168c0c4a9c5bba9e04afea5aad5cc7dc2bb (patch) | |
| tree | 8ebf935ce774bc4229a4d85e2e6675da192056ca /gcc | |
| parent | 803cb0b5c9ff81ba0b4ec018fff529a9b7cf43f2 (diff) | |
| download | gcc-d1fe6168c0c4a9c5bba9e04afea5aad5cc7dc2bb.zip gcc-d1fe6168c0c4a9c5bba9e04afea5aad5cc7dc2bb.tar.gz gcc-d1fe6168c0c4a9c5bba9e04afea5aad5cc7dc2bb.tar.bz2 | |
m68k.h (EXTRA_CONSTRAINT): add 'U' for register offset addressing.
* config/m68k/m68k.h(EXTRA_CONSTRAINT): add 'U' for register offset
addressing.
* config/m68k/m68k.md: Add 'U,U' alternative to ColdFire variants of
movsi,movhi,movqi insn patterns.
From-SVN: r82420
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/m68k/m68k.h | 11 | ||||
| -rw-r--r-- | gcc/config/m68k/m68k.md | 12 |
3 files changed, 22 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 055155c..ca2b422 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2004-05-29 Peter Barada <peter@the-baradas.com> + + * config/m68k/m68k.h(EXTRA_CONSTRAINT): add 'U' for register offset + addressing. + * config/m68k/m68k.md: Add 'U,U' alternative to ColdFire variants of + movsi,movhi,movqi insn patterns. + 2005-05-28 Andrew Pinski <pinskia@physics.uc.edu> * c-semantics.c (emit_local_var): Remove code for DECL_INITIAL. diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h index 522f0dc..c7cc76b 100644 --- a/gcc/config/m68k/m68k.h +++ b/gcc/config/m68k/m68k.h @@ -735,7 +735,8 @@ extern enum reg_class regno_reg_class[]; `Q' means address register indirect addressing mode. `S' is for operands that satisfy 'm' when -mpcrel is in effect. - `T' is for operands that satisfy 's' when -mpcrel is not in effect. */ + `T' is for operands that satisfy 's' when -mpcrel is not in effect. + `U' is for register offset addressing. */ #define EXTRA_CONSTRAINT(OP,CODE) \ (((CODE) == 'S') \ @@ -755,7 +756,13 @@ extern enum reg_class regno_reg_class[]; ? (GET_CODE (OP) == MEM \ && GET_CODE (XEXP (OP, 0)) == REG) \ : \ - 0))) + (((CODE) == 'U') \ + ? (GET_CODE (OP) == MEM \ + && GET_CODE (XEXP (OP, 0)) == PLUS \ + && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \ + && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \ + : \ + 0)))) /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index e674ca2..2603195 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -676,8 +676,8 @@ }) (define_insn "" - [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g") - (match_operand:SI 1 "general_operand" "g,r<Q>"))] + [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g,U") + (match_operand:SI 1 "general_operand" "g,r<Q>,U"))] "TARGET_COLDFIRE" "* return output_move_simode (operands);") @@ -706,8 +706,8 @@ "* return output_move_himode (operands);") (define_insn "" - [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g") - (match_operand:HI 1 "general_operand" "g,r<Q>"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g,U") + (match_operand:HI 1 "general_operand" "g,r<Q>,U"))] "TARGET_COLDFIRE" "* return output_move_himode (operands);") @@ -742,8 +742,8 @@ "* return output_move_qimode (operands);") (define_insn "" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,d*a") - (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))] + [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,U,d*a") + (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,U,di*a"))] "TARGET_COLDFIRE" "* return output_move_qimode (operands);") |