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| author | Roger Sayle <roger@nextmovesoftware.com> | 2023-06-23 15:23:20 +0100 |
|---|---|---|
| committer | Roger Sayle <roger@nextmovesoftware.com> | 2023-06-23 15:23:20 +0100 |
| commit | d0e891406b16dc28905717de2333f5637cf71d3e (patch) | |
| tree | e66942d91a5d39cf396f552e102080c2d558255e /gcc | |
| parent | 2acbbf41d4c2a3362991863ce265041f9a2feee4 (diff) | |
| download | gcc-d0e891406b16dc28905717de2333f5637cf71d3e.zip gcc-d0e891406b16dc28905717de2333f5637cf71d3e.tar.gz gcc-d0e891406b16dc28905717de2333f5637cf71d3e.tar.bz2 | |
Improved SUBREG simplifications in simplify-rtx.cc's simplify_subreg.
An x86 backend improvement that I'm working results in combine attempting
to recognize:
(set (reg:DI 87 [ xD.2846 ])
(ior:DI (subreg:DI (ashift:TI (zero_extend:TI (reg:DI 92))
(const_int 64 [0x40])) 0)
(reg:DI 91)))
where the lowpart SUBREG has difficulty seeing through the (hi<<64)
that the lowpart must be zero. Rather than workaround this in the
backend, the better fix is to teach simplify-rtx that
lowpart((hi<<64)|lo) -> lo and highpart((hi<<64)|lo) -> hi, so that
all backends benefit. Reducing the number of places where the
middle-end generates a SUBREG of something other than REG is a
good thing.
On x86_64-pc-linux-gnu, the testcase pr78904-1b.c FAILs with this patch,
due to changes in expected/canonical RTL, for which a backend patch to
i386.md has already been provisionally approved.
2023-06-23 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* simplify-rtx.cc (simplify_subreg): Optimize lowpart SUBREGs
of ASHIFT to const0_rtx with sufficiently large shift count.
Optimize highpart SUBREGs of ASHIFT as the shift operand when
the shift count is the correct offset. Optimize SUBREGs of
multi-word logic operations if the SUBREGs of both operands
can be simplified.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/simplify-rtx.cc | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index 1b58144..99cbdd4 100644 --- a/gcc/simplify-rtx.cc +++ b/gcc/simplify-rtx.cc @@ -7758,6 +7758,38 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op, return CONST0_RTX (outermode); } + /* Optimize SUBREGS of scalar integral ASHIFT by a valid constant. */ + if (GET_CODE (op) == ASHIFT + && SCALAR_INT_MODE_P (innermode) + && CONST_INT_P (XEXP (op, 1)) + && INTVAL (XEXP (op, 1)) > 0 + && known_gt (GET_MODE_BITSIZE (innermode), INTVAL (XEXP (op, 1)))) + { + HOST_WIDE_INT val = INTVAL (XEXP (op, 1)); + /* A lowpart SUBREG of a ASHIFT by a constant may fold to zero. */ + if (known_eq (subreg_lowpart_offset (outermode, innermode), byte) + && known_le (GET_MODE_BITSIZE (outermode), val)) + return CONST0_RTX (outermode); + /* Optimize the highpart SUBREG of a suitable ASHIFT (ZERO_EXTEND). */ + if (GET_CODE (XEXP (op, 0)) == ZERO_EXTEND + && GET_MODE (XEXP (XEXP (op, 0), 0)) == outermode + && known_eq (GET_MODE_BITSIZE (outermode), val) + && known_eq (GET_MODE_BITSIZE (innermode), 2 * val) + && known_eq (subreg_highpart_offset (outermode, innermode), byte)) + return XEXP (XEXP (op, 0), 0); + } + + /* Attempt to simplify WORD_MODE SUBREGs of bitwise expressions. */ + if (outermode == word_mode + && (GET_CODE (op) == IOR || GET_CODE (op) == XOR || GET_CODE (op) == AND) + && SCALAR_INT_MODE_P (innermode)) + { + rtx op0 = simplify_subreg (outermode, XEXP (op, 0), innermode, byte); + rtx op1 = simplify_subreg (outermode, XEXP (op, 1), innermode, byte); + if (op0 && op1) + return simplify_gen_binary (GET_CODE (op), outermode, op0, op1); + } + scalar_int_mode int_outermode, int_innermode; if (is_a <scalar_int_mode> (outermode, &int_outermode) && is_a <scalar_int_mode> (innermode, &int_innermode) |