aboutsummaryrefslogtreecommitdiff
path: root/gcc
diff options
context:
space:
mode:
authorRobin Dapp <rdapp@ventanamicro.com>2024-12-12 10:33:28 +0100
committerRobin Dapp <rdapp@ventanamicro.com>2024-12-13 10:08:11 +0100
commitcfdab86f20f6e77d9c8bf982989f78ef975c7611 (patch)
tree79a2bde237f87bca871ac4d48394abc806ab3d66 /gcc
parenta8e07f98dfaa0f61db84a80ee77c5b4f964a4428 (diff)
downloadgcc-cfdab86f20f6e77d9c8bf982989f78ef975c7611.zip
gcc-cfdab86f20f6e77d9c8bf982989f78ef975c7611.tar.gz
gcc-cfdab86f20f6e77d9c8bf982989f78ef975c7611.tar.bz2
RISC-V: Emit vector shift pattern for const_vector [PR117353].
In PR117353 and PR117878 we expand a const vector during reload. For this we use an unpredicated left shift. Normally an insn like this is split but as we introduce it late and cannot create pseudos anymore it remains unpredicated and is not recognized by the vsetvl pass (where we expect all insns to be in predicated RVV format). This patch directly emits a predicated shift instead. We could distinguish between !lra_in_progress and lra_in_progress and emit an unpredicated shift in the former case but we're not very likely to optimize it anyway so it doesn't seem worth it. PR target/117353 PR target/117878 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Use predicated instead of simple shift. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr117353.c: New test.
Diffstat (limited to 'gcc')
-rw-r--r--gcc/config/riscv/riscv-v.cc8
-rw-r--r--gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117353.c29
2 files changed, 34 insertions, 3 deletions
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 47bc0255..2530fd9 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1439,9 +1439,11 @@ expand_const_vector (rtx target, rtx src)
rtx shift_count
= gen_int_mode (exact_log2 (builder.npatterns ()),
builder.inner_mode ());
- rtx tmp1 = expand_simple_binop (builder.mode (), LSHIFTRT,
- vid, shift_count, NULL_RTX,
- false, OPTAB_DIRECT);
+ rtx tmp1 = gen_reg_rtx (builder.mode ());
+ rtx shift_ops[] = {tmp1, vid, shift_count};
+ emit_vlmax_insn (code_for_pred_scalar
+ (LSHIFTRT, builder.mode ()), BINARY_OP,
+ shift_ops);
/* Step 3: Generate tmp2 = tmp1 * step.  */
rtx tmp2 = gen_reg_rtx (builder.mode ());
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117353.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117353.c
new file mode 100644
index 0000000..135a001
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117353.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gcv_zvl256b -mabi=lp64d" } */
+
+int *b;
+
+inline void c (char *d, int e)
+{
+ d[0] = 0;
+ d[1] = e;
+}
+
+void f ();
+
+void h ()
+{
+ for (;;)
+ {
+ char *a;
+ long g = 8;
+ while (g)
+ {
+ c (a, *b);
+ b++;
+ a += 2;
+ g--;
+ }
+ f ();
+ }
+}