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| author | Pan Li <pan2.li@intel.com> | 2024-12-20 14:44:10 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2024-12-22 10:36:46 +0800 |
| commit | cf59bf844037ae952f5058d0fd49e1f4f0cf907e (patch) | |
| tree | 8249a015e1eb1a9490a6b1c5ea7d0b4c7960ad55 /gcc | |
| parent | ae3e783e23a30e9856e1504c5542acbcb0050e67 (diff) | |
| download | gcc-cf59bf844037ae952f5058d0fd49e1f4f0cf907e.zip gcc-cf59bf844037ae952f5058d0fd49e1f4f0cf907e.tar.gz gcc-cf59bf844037ae952f5058d0fd49e1f4f0cf907e.tar.bz2 | |
RISC-V: Fix the the operand alignment for strided load/store pattern [NFC]
Just notice the unalignment operand for strided load/store pattern when
bugfix the strided load/store memory alias, would like to make it align.
gcc/ChangeLog:
* config/riscv/autovec.md: Align the operand for strided
load/store pattern.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/autovec.md | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 2529dc7..88c0f00 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -2903,7 +2903,7 @@ ;; == Strided Load/Store ;; ========================================================================= (define_expand "mask_len_strided_load_<mode>" - [(match_operand:V_VLS 0 "register_operand") + [(match_operand:V_VLS 0 "register_operand") (match_operand 1 "pmode_reg_or_0_operand") (match_operand 2 "pmode_reg_or_0_operand") (match_operand:<VM> 3 "vector_mask_operand") @@ -2919,7 +2919,7 @@ (define_expand "mask_len_strided_store_<mode>" [(match_operand 0 "pmode_reg_or_0_operand") (match_operand 1 "pmode_reg_or_0_operand") - (match_operand:V_VLS 2 "register_operand") + (match_operand:V_VLS 2 "register_operand") (match_operand:<VM> 3 "vector_mask_operand") (match_operand 4 "autovec_length_operand") (match_operand 5 "const_0_operand")] |