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author | Vladimir Makarov <vmakarov@redhat.com> | 2014-05-29 17:37:23 +0000 |
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committer | Vladimir Makarov <vmakarov@gcc.gnu.org> | 2014-05-29 17:37:23 +0000 |
commit | cc8849a1597bb12c16a990bfed6a3b685952d493 (patch) | |
tree | 5655e5962c0abad946b13ad9235bc659e50a60b5 /gcc | |
parent | e4c03722c501d01f0ba75e72318377e5a85b06ce (diff) | |
download | gcc-cc8849a1597bb12c16a990bfed6a3b685952d493.zip gcc-cc8849a1597bb12c16a990bfed6a3b685952d493.tar.gz gcc-cc8849a1597bb12c16a990bfed6a3b685952d493.tar.bz2 |
re PR rtl-optimization/61325 (aarch64_be build fails)
2014-05-29 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/61325
* lra-constraints.c (process_address): Rename to
process_address_1.
(process_address): New function.
2014-05-29 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/61325
* gcc.target/aarch64/pr61325.c: New.
From-SVN: r211061
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 7 | ||||
-rw-r--r-- | gcc/lra-constraints.c | 23 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr61325.c | 19 |
4 files changed, 51 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 273bf64..18335a9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2014-05-29 Vladimir Makarov <vmakarov@redhat.com> + + PR rtl-optimization/61325 + * lra-constraints.c (process_address): Rename to + process_address_1. + (process_address): New function. + 2014-05-29 Alan Lawrence <alan.lawrence@arm.com> * config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers, diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c index 2df841a..69ffdcd 100644 --- a/gcc/lra-constraints.c +++ b/gcc/lra-constraints.c @@ -2784,9 +2784,14 @@ equiv_address_substitution (struct address_info *ad) Add reloads to the lists *BEFORE and *AFTER. We might need to add reloads to *AFTER because of inc/dec, {pre, post} modify in the - address. Return true for any RTL change. */ + address. Return true for any RTL change. + + The function is a helper function which does not produce all + transformations which can be necessary. It does just basic steps. + To do all necessary transformations use function + process_address. */ static bool -process_address (int nop, rtx *before, rtx *after) +process_address_1 (int nop, rtx *before, rtx *after) { struct address_info ad; rtx new_reg; @@ -2986,6 +2991,18 @@ process_address (int nop, rtx *before, rtx *after) return true; } +/* Do address reloads until it is necessary. Use process_address_1 as + a helper function. Return true for any RTL changes. */ +static bool +process_address (int nop, rtx *before, rtx *after) +{ + bool res = false; + + while (process_address_1 (nop, before, after)) + res = true; + return res; +} + /* Emit insns to reload VALUE into a new register. VALUE is an auto-increment or auto-decrement RTX whose operand is a register or memory location; so reloading involves incrementing that location. @@ -3270,7 +3287,7 @@ curr_insn_transform (void) change_p = true; lra_update_dup (curr_id, i); } - + if (change_p) /* If we've changed the instruction then any alternative that we chose previously may no longer be valid. */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 048b02a..8bf5b1f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2014-05-29 Vladimir Makarov <vmakarov@redhat.com> + + PR rtl-optimization/61325 + * gcc.target/aarch64/pr61325.c: New. + 2014-05-29 Alan Lawrence <alan.lawrence@arm.com> gcc.target/arm/simd/vextQf32_1.c: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/pr61325.c b/gcc/testsuite/gcc.target/aarch64/pr61325.c new file mode 100644 index 0000000..45ece53 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr61325.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +typedef unsigned int wchar_t; +typedef long unsigned int size_t; + +size_t +wcstombs(char *s , const wchar_t *pwcs , size_t n) +{ + int count = 0; + + if (n != 0) { + do { + if ((*s++ = (char) *pwcs++) == 0) + break; + count++; + } while (--n != 0); + } + return count; +} |