md.texi: Update documentation of MIPS constraints.

	* doc/md.texi: Update documentation of MIPS constraints.
	* config/mips/constraints.md: New file.
	* config/mips/mips.md: Include it.
	* config/mips/mips.c (mips_char_to_class): Delete.
	(override_options): Don't initialize mips_char_to_class.
	* config/mips/mips.h (mips_char_to_class): Delete.
	(REG_CLASS_FROM_LETTER): Delete.
	(CONST_OK_FOR_LETTER_P): Delete.
	(CONST_DOUBLE_OK_FOR_LETTER_P): Delete.
	(EXTRA_CONSTRAINT_Y): Delete.
	(EXTRA_CONSTRAINT_STR): Delete.
	(CONSTRAINT_LEN): Delete.
	(EXTRA_MEMORY_CONSTRAINT): Delete.

From-SVN: r111868

6 files changed, 237 insertions, 192 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1f5ecd5..9b1fb91 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,19 @@
+2006-03-09  Richard Sandiford  <richard@codesourcery.com>
+
+	* doc/md.texi: Update documentation of MIPS constraints.
+	* config/mips/constraints.md: New file.
+	* config/mips/mips.md: Include it.
+	* config/mips/mips.c (mips_char_to_class): Delete.
+	(override_options): Don't initialize mips_char_to_class.
+	* config/mips/mips.h (mips_char_to_class): Delete.
+	(REG_CLASS_FROM_LETTER): Delete.
+	(CONST_OK_FOR_LETTER_P): Delete.
+	(CONST_DOUBLE_OK_FOR_LETTER_P): Delete.
+	(EXTRA_CONSTRAINT_Y): Delete.
+	(EXTRA_CONSTRAINT_STR): Delete.
+	(CONSTRAINT_LEN): Delete.
+	(EXTRA_MEMORY_CONSTRAINT): Delete.
+
 2006-03-09  Diego Novillo  <dnovillo@redhat.com>
 
 	* tree-cfg.c (move_block_to_fn): Remove the statements from the
diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md
new file mode 100644
index 0000000..711aa15
--- /dev/null
+++ b/gcc/config/mips/constraints.md
@@ -0,0 +1,195 @@
+;; Constraint definitions for MIPS.
+;; Copyright (C) 2006 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+;; Boston, MA 02110-1301, USA.
+
+;; Register constraints
+
+(define_register_constraint "d" "BASE_REG_CLASS"
+  "An address register.  This is equivalent to @code{r} unless
+   generating MIPS16 code.")
+
+(define_register_constraint "t" "T_REG"
+  "@internal")
+
+(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
+  "A floating-point register (if available).")
+
+(define_register_constraint "h" "HI_REG"
+  "The @code{hi} register.")
+
+(define_register_constraint "l" "LO_REG"
+  "The @code{lo} register.")
+
+(define_register_constraint "x" "MD_REGS"
+  "The @code{hi} and @code{lo} registers.")
+
+(define_register_constraint "b" "ALL_REGS"
+  "@internal")
+
+(define_register_constraint "c" "TARGET_ABICALLS ? PIC_FN_ADDR_REG
+				 : TARGET_MIPS16 ? M16_NA_REGS
+				 : GR_REGS"
+  "A register suitable for use in an indirect jump.  This will always be
+   @code{$25} for @option{-mabicalls}.")
+
+(define_register_constraint "e" "LEA_REGS"
+  "@internal")
+
+(define_register_constraint "j" "PIC_FN_ADDR_REG"
+  "@internal")
+
+(define_register_constraint "v" "V1_REG"
+  "@internal")
+
+(define_register_constraint "y" "GR_REGS"
+  "Equivalent to @code{r}; retained for backwards compatibility.")
+
+(define_register_constraint "z" "ST_REGS"
+  "A floating-point condition code register.")
+
+(define_register_constraint "A" "DSP_ACC_REGS"
+  "@internal")
+
+(define_register_constraint "a" "ACC_REGS"
+  "@internal")
+
+(define_register_constraint "B" "COP0_REGS"
+  "@internal")
+
+(define_register_constraint "C" "COP2_REGS"
+  "@internal")
+
+(define_register_constraint "D" "COP3_REGS"
+  "@internal")
+
+;; Integer constraints
+
+(define_constraint "I"
+  "A signed 16-bit constant (for arithmetic instructions)."
+  (and (match_code "const_int")
+       (match_test "SMALL_OPERAND (ival)")))
+
+(define_constraint "J"
+  "Integer zero."
+  (and (match_code "const_int")
+       (match_test "ival == 0")))
+
+(define_constraint "K"
+  "An unsigned 16-bit constant (for logic instructions)."
+  (and (match_code "const_int")
+       (match_test "SMALL_OPERAND_UNSIGNED (ival)")))
+ 
+(define_constraint "L"
+  "A signed 32-bit constant in which the lower 16 bits are zero.
+   Such constants can be loaded using @code{lui}."
+  (and (match_code "const_int")
+       (match_test "LUI_OPERAND (ival)")))
+
+(define_constraint "M"
+  "A constant that cannot be loaded using @code{lui}, @code{addiu}
+   or @code{ori}."
+  (and (match_code "const_int")
+       (match_test "!SMALL_OPERAND (ival)")
+       (match_test "!SMALL_OPERAND_UNSIGNED (ival)")
+       (match_test "!LUI_OPERAND (ival)")))
+
+(define_constraint "N"
+  "A constant in the range -65535 to -1 (inclusive)."
+  (and (match_code "const_int")
+       (match_test "ival >= -0xffff && ival < 0")))
+
+(define_constraint "O"
+  "A signed 15-bit constant."
+  (and (match_code "const_int")
+       (match_test "ival >= -0x4000 && ival < 0x4000")))
+
+(define_constraint "P"
+  "A constant in the range 1 to 65535 (inclusive)."
+  (and (match_code "const_int")
+       (match_test "ival > 0 && ival < 0x10000")))
+
+;; Floating-point constraints
+
+(define_constraint "G"
+  "Floating-point zero."
+  (and (match_code "const_double")
+       (match_test "op == CONST0_RTX (mode)")))
+
+;; General constraints
+
+(define_constraint "Q"
+  "@internal"
+  (match_operand 0 "const_arith_operand"))
+
+(define_memory_constraint "R"
+  "An address that can be used in a non-macro load or store."
+  (and (match_code "mem")
+       (match_test "mips_fetch_insns (op) == 1")))
+
+(define_constraint "S"
+  "@internal
+   A constant call address."
+  (and (match_operand 0 "call_insn_operand")
+       (match_test "CONSTANT_P (op)")))
+
+(define_constraint "T"
+  "@internal
+   A constant @code{move_operand} that cannot be safely loaded into @code{$25}
+   using @code{la}."
+  (and (match_operand 0 "move_operand")
+       (match_test "CONSTANT_P (op)")
+       (match_test "mips_dangerous_for_la25_p (op)")))
+
+(define_constraint "U"
+  "@internal
+   A constant @code{move_operand} that can be safely loaded into @code{$25}
+   using @code{la}."
+  (and (match_operand 0 "move_operand")
+       (match_test "CONSTANT_P (op)")
+       (match_test "!mips_dangerous_for_la25_p (op)")))
+
+(define_memory_constraint "W"
+  "@internal
+   A memory address based on a member of @code{BASE_REG_CLASS}.  This is
+   true for all non-mips16 references (although it can sometimes be implicit
+   if @samp{!TARGET_EXPLICIT_RELOCS}).  For MIPS16, it excludes stack and
+   constant-pool references."
+  (and (match_code "mem")
+       (match_operand 0 "memory_operand")
+       (ior (match_test "!TARGET_MIPS16")
+	    (and (not (match_operand 0 "stack_operand"))
+		 (not (match_test "CONSTANT_P (XEXP (op, 0))"))))))
+
+(define_constraint "YG"
+  "@internal
+   A vector zero."
+  (and (match_code "const_vector")
+       (match_test "op == CONST0_RTX (mode)")))
+
+(define_constraint "YA"
+  "@internal
+   An unsigned 6-bit constant."
+  (and (match_code "const_int")
+       (match_test "UIMM6_OPERAND (ival)")))
+
+(define_constraint "YB"
+  "@internal
+   A signed 10-bit constant."
+  (and (match_code "const_int")
+       (match_test "IMM10_OPERAND (ival)")))
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 82db1ac..aed07e5 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -690,9 +690,6 @@ const enum reg_class mips_regno_to_class[] =
   ALL_REGS,	ALL_REGS,	ALL_REGS,	ALL_REGS
 };
 
-/* Map register constraint character to register class.  */
-enum reg_class mips_char_to_class[256];
-
 /* Table of machine dependent attributes.  */
 const struct attribute_spec mips_attribute_table[] =
 {
@@ -4844,27 +4841,6 @@ override_options (void)
   mips_print_operand_punct['+'] = 1;
   mips_print_operand_punct['~'] = 1;
 
-  mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
-  mips_char_to_class['t'] = T_REG;
-  mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
-  mips_char_to_class['h'] = HI_REG;
-  mips_char_to_class['l'] = LO_REG;
-  mips_char_to_class['x'] = MD_REGS;
-  mips_char_to_class['b'] = ALL_REGS;
-  mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
-			     TARGET_MIPS16 ? M16_NA_REGS :
-			     GR_REGS);
-  mips_char_to_class['e'] = LEA_REGS;
-  mips_char_to_class['j'] = PIC_FN_ADDR_REG;
-  mips_char_to_class['v'] = V1_REG;
-  mips_char_to_class['y'] = GR_REGS;
-  mips_char_to_class['z'] = ST_REGS;
-  mips_char_to_class['B'] = COP0_REGS;
-  mips_char_to_class['C'] = COP2_REGS;
-  mips_char_to_class['D'] = COP3_REGS;
-  mips_char_to_class['A'] = DSP_ACC_REGS;
-  mips_char_to_class['a'] = ACC_REGS;
-
   /* Set up array to map GCC register number to debug register number.
      Ignore the special purpose register numbers.  */
 
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 8ebb3c5..8a993e0 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1636,35 +1636,6 @@ extern const enum reg_class mips_regno_to_class[];
 
 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
 
-/* REGISTER AND CONSTANT CLASSES */
-
-/* Get reg_class from a letter such as appears in the machine
-   description.
-
-   DEFINED REGISTER CLASSES:
-
-   'd'  General (aka integer) registers
-        Normally this is GR_REGS, but in mips16 mode this is M16_REGS
-   'y'  General registers (in both mips16 and non mips16 mode)
-   'e'	Effective address registers (general registers except $25)
-   't'  mips16 temporary register ($24)
-   'f'	Floating point registers
-   'h'	Hi register
-   'l'	Lo register
-   'v'	$v1 only
-   'x'	Multiply/divide registers
-   'z'	FP Status register
-   'B'  Cop0 register
-   'C'  Cop2 register
-   'D'  Cop3 register
-   'A'  DSP accumulator registers
-   'a'  MD registers and DSP accumulator registers
-   'b'	All registers */
-
-extern enum reg_class mips_char_to_class[256];
-
-#define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
-
 /* True if VALUE is an unsigned 6-bit number.  */
 
 #define UIMM6_OPERAND(VALUE) \
@@ -1704,117 +1675,6 @@ extern enum reg_class mips_char_to_class[256];
 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
 
-/* The letters I, J, K, L, M, N, O, and P in a register constraint
-   string can be used to stand for particular ranges of immediate
-   operands.  This macro defines what the ranges are.  C is the
-   letter, and VALUE is a constant value.  Return 1 if VALUE is
-   in the range specified by C.  */
-
-/* For MIPS:
-
-   `I'	is used for the range of constants an arithmetic insn can
-	actually contain (16 bits signed integers).
-
-   `J'	is used for the range which is just zero (i.e., $r0).
-
-   `K'	is used for the range of constants a logical insn can actually
-	contain (16 bit zero-extended integers).
-
-   `L'	is used for the range of constants that be loaded with lui
-	(i.e., the bottom 16 bits are zero).
-
-   `M'	is used for the range of constants that take two words to load
-	(i.e., not matched by `I', `K', and `L').
-
-   `N'	is used for negative 16 bit constants other than -65536.
-
-   `O'	is a 15 bit signed integer.
-
-   `P'	is used for positive 16 bit constants.  */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C)					\
-  ((C) == 'I' ? SMALL_OPERAND (VALUE)					\
-   : (C) == 'J' ? ((VALUE) == 0)					\
-   : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE)			\
-   : (C) == 'L' ? LUI_OPERAND (VALUE)					\
-   : (C) == 'M' ? (!SMALL_OPERAND (VALUE)				\
-		   && !SMALL_OPERAND_UNSIGNED (VALUE)			\
-		   && !LUI_OPERAND (VALUE))				\
-   : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
-   : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
-   : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0))	\
-   : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
-   Here VALUE is the CONST_DOUBLE rtx itself.  */
-
-/* For MIPS
-
-  'G'	: Floating point 0 */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)				\
-  ((C) == 'G'								\
-   && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
-
-/* Letters in the range `Q' through `U' may be defined in a
-   machine-dependent fashion to stand for arbitrary operand types.
-   The machine description macro `EXTRA_CONSTRAINT' is passed the
-   operand as its first argument and the constraint letter as its
-   second operand.
-
-   `Q' is for signed 16-bit constants.
-   `R' is for single-instruction memory references.  Note that this
-	 constraint has often been used in linux and glibc code.
-   `S' is for legitimate constant call addresses.
-   `T' is for constant move_operands that cannot be safely loaded into $25.
-   `U' is for constant move_operands that can be safely loaded into $25.
-   `W' is for memory references that are based on a member of BASE_REG_CLASS.
-	 This is true for all non-mips16 references (although it can sometimes
-	 be indirect if !TARGET_EXPLICIT_RELOCS).  For mips16, it excludes
-	 stack and constant-pool references.
-   `YG' is for 0 valued vector constants.
-   `YA' is for unsigned 6-bit constants.
-   `YB' is for signed 10-bit constants.  */
-
-#define EXTRA_CONSTRAINT_Y(OP,STR)					\
-  (((STR)[1] == 'G')	  ? (GET_CODE (OP) == CONST_VECTOR		\
-			     && (OP) == CONST0_RTX (GET_MODE (OP)))	\
-   : ((STR)[1] == 'A')	  ? (GET_CODE (OP) == CONST_INT			\
-			     && UIMM6_OPERAND (INTVAL (OP)))		\
-   : ((STR)[1] == 'B')	  ? (GET_CODE (OP) == CONST_INT			\
-			     && IMM10_OPERAND (INTVAL (OP)))		\
-   : FALSE)
-
-
-#define EXTRA_CONSTRAINT_STR(OP,CODE,STR)				\
-  (((CODE) == 'Q')	  ? const_arith_operand (OP, VOIDmode)		\
-   : ((CODE) == 'R')	  ? (MEM_P (OP)					\
-			     && mips_fetch_insns (OP) == 1)		\
-   : ((CODE) == 'S')	  ? (CONSTANT_P (OP)				\
-			     && call_insn_operand (OP, VOIDmode))	\
-   : ((CODE) == 'T')	  ? (CONSTANT_P (OP)				\
-			     && move_operand (OP, VOIDmode)		\
-			     && mips_dangerous_for_la25_p (OP))		\
-   : ((CODE) == 'U')	  ? (CONSTANT_P (OP)				\
-			     && move_operand (OP, VOIDmode)		\
-			     && !mips_dangerous_for_la25_p (OP))	\
-   : ((CODE) == 'W')	  ? (MEM_P (OP)					\
-			     && memory_operand (OP, VOIDmode)		\
-			     && (!TARGET_MIPS16				\
-				 || (!stack_operand (OP, VOIDmode)	\
-				     && !CONSTANT_P (XEXP (OP, 0)))))	\
-   : ((CODE) == 'Y')	  ? EXTRA_CONSTRAINT_Y (OP, STR)		\
-   : FALSE)
-
-/* Y is the only multi-letter constraint, and has length 2.  */
-
-#define CONSTRAINT_LEN(C,STR)						\
-  (((C) == 'Y') ? 2							\
-   : DEFAULT_CONSTRAINT_LEN (C, STR))
-
-/* Say which of the above are memory constraints.  */
-#define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
-
 #define PREFERRED_RELOAD_CLASS(X,CLASS)					\
   mips_preferred_reload_class (X, CLASS)
 
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 3d55857..23677f0 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -146,6 +146,7 @@
 )
 
 (include "predicates.md")
+(include "constraints.md")
 
 ;; ....................
 ;;
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 993fb11..0fc2265 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -2368,68 +2368,65 @@ Memory addressed using the small base register ($sb).
 $r1h
 @end table
 
-@item MIPS---@file{config/mips/mips.h}
+@item MIPS---@file{config/mips/constraints.md}
 @table @code
 @item d
-General-purpose integer register
+An address register.  This is equivalent to @code{r} unless
+generating MIPS16 code.
 
 @item f
-Floating-point register (if available)
+A floating-point register (if available).
 
 @item h
-@samp{Hi} register
+The @code{hi} register.
 
 @item l
-@samp{Lo} register
+The @code{lo} register.
 
 @item x
-@samp{Hi} or @samp{Lo} register
+The @code{hi} and @code{lo} registers.
+
+@item c
+A register suitable for use in an indirect jump.  This will always be
+@code{$25} for @option{-mabicalls}.
 
 @item y
-General-purpose integer register
+Equivalent to @code{r}; retained for backwards compatibility.
 
 @item z
-Floating-point status register
+A floating-point condition code register.
 
 @item I
-Signed 16-bit constant (for arithmetic instructions)
+A signed 16-bit constant (for arithmetic instructions).
 
 @item J
-Zero
+Integer zero.
 
 @item K
-Zero-extended 16-bit constant (for logic instructions)
+An unsigned 16-bit constant (for logic instructions).
 
 @item L
-Constant with low 16 bits zero (can be loaded with @code{lui})
+A signed 32-bit constant in which the lower 16 bits are zero.
+Such constants can be loaded using @code{lui}.
 
 @item M
-32-bit constant which requires two instructions to load (a constant
-which is not @samp{I}, @samp{K}, or @samp{L})
+A constant that cannot be loaded using @code{lui}, @code{addiu}
+or @code{ori}.
 
 @item N
-Negative 16-bit constant
+A constant in the range -65535 to -1 (inclusive).
 
 @item O
-Exact power of two
+A signed 15-bit constant.
 
 @item P
-Positive 16-bit constant
+A constant in the range 1 to 65535 (inclusive).
 
 @item G
-Floating point zero
-
-@item Q
-Memory reference that can be loaded with more than one instruction
-(@samp{m} is preferable for @code{asm} statements)
+Floating-point zero.
 
 @item R
-Memory reference that can be loaded with one instruction
-(@samp{m} is preferable for @code{asm} statements)
-
-@item S
-Memory reference in external OSF/rose PIC format
-(@samp{m} is preferable for @code{asm} statements)
+An address that can be used in a non-macro load or store.
 @end table
 
 @item Motorola 680x0---@file{config/m68k/m68k.h}