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| author | Kaushik Phatak <kaushik.phatak@kpitcummins.com> | 2010-12-14 07:03:36 +0000 |
|---|---|---|
| committer | Kaushik Phatak <kaushikp@gcc.gnu.org> | 2010-12-14 07:03:36 +0000 |
| commit | c7e1fa82502f98b4ac9c6e576345debf6b56a654 (patch) | |
| tree | cfe83b6fc75607a40ae5d0b6130f56d104b7fde4 /gcc | |
| parent | 05d556e8371b90c5de4175aa737a7ad83726eeee (diff) | |
| download | gcc-c7e1fa82502f98b4ac9c6e576345debf6b56a654.zip gcc-c7e1fa82502f98b4ac9c6e576345debf6b56a654.tar.gz gcc-c7e1fa82502f98b4ac9c6e576345debf6b56a654.tar.bz2 | |
h8300.md (define_split): Add condition for "and with single_zero" splitter to handle 16-bit const operands.
* config/h8300/h8300.md (define_split) : Add condition for
"and with single_zero" splitter to handle 16-bit const operands.
* config/h8300/h8300.md (define_split) : Add condition for
"ior with single_one" splitter to handle 16-bit const operands.
* config/h8300/h8300.md (define_split) : Add condition for
"xor with single_one" splitter to handle 16-bit const operands.
* testsuite/gcc.dg/h8300-bit-insn-ice.c: New.
From-SVN: r167789
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/h8300/h8300.md | 39 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/h8300-bit-insn-ice.c | 39 |
3 files changed, 82 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9b20492..8d03fce 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2010-12-14 Kaushik Phatak <kaushik.phatak@kpitcummins.com> + + * config/h8300/h8300.md (define_split) : Add condition for + "and with single_zero" splitter to handle 16-bit const operands. + * config/h8300/h8300.md (define_split) : Add condition for + "ior with single_one" splitter to handle 16-bit const operands. + * config/h8300/h8300.md (define_split) : Add condition for + "xor with single_one" splitter to handle 16-bit const operands. + * testsuite/gcc.dg/h8300-bit-insn-ice.c: New. + 2010-12-13 Jan Hubicka <jh@suse.cz> PR middle-end/45388 diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md index 513ad4c..21ab391 100644 --- a/gcc/config/h8300/h8300.md +++ b/gcc/config/h8300/h8300.md @@ -1779,8 +1779,17 @@ (and:QI (match_dup 1) (match_dup 2)))] { - operands[0] = adjust_address (operands[0], QImode, 1); - operands[1] = adjust_address (operands[1], QImode, 1); + if (abs (INTVAL (operands[2])) > 0xFF) + { + operands[0] = adjust_address (operands[0], QImode, 0); + operands[1] = adjust_address (operands[1], QImode, 0); + operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8); + } + else + { + operands[0] = adjust_address (operands[0], QImode, 1); + operands[1] = adjust_address (operands[1], QImode, 1); + } }) (define_insn "bclrhi_msx" @@ -1910,8 +1919,17 @@ (ior:QI (match_dup 1) (match_dup 2)))] { - operands[0] = adjust_address (operands[0], QImode, 1); - operands[1] = adjust_address (operands[1], QImode, 1); + if (abs (INTVAL (operands[2])) > 0xFF) + { + operands[0] = adjust_address (operands[0], QImode, 0); + operands[1] = adjust_address (operands[1], QImode, 0); + operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8); + } + else + { + operands[0] = adjust_address (operands[0], QImode, 1); + operands[1] = adjust_address (operands[1], QImode, 1); + } }) (define_insn "bsethi_msx" @@ -1976,8 +1994,17 @@ (xor:QI (match_dup 1) (match_dup 2)))] { - operands[0] = adjust_address (operands[0], QImode, 1); - operands[1] = adjust_address (operands[1], QImode, 1); + if (abs (INTVAL (operands[2])) > 0xFF) + { + operands[0] = adjust_address (operands[0], QImode, 0); + operands[1] = adjust_address (operands[1], QImode, 0); + operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8); + } + else + { + operands[0] = adjust_address (operands[0], QImode, 1); + operands[1] = adjust_address (operands[1], QImode, 1); + } }) (define_insn "bnothi_msx" diff --git a/gcc/testsuite/gcc.dg/h8300-bit-insn-ice.c b/gcc/testsuite/gcc.dg/h8300-bit-insn-ice.c new file mode 100644 index 0000000..442dc4b --- /dev/null +++ b/gcc/testsuite/gcc.dg/h8300-bit-insn-ice.c @@ -0,0 +1,39 @@ +/* { dg-skip-if "" { "h8300*-*-*" } "*" "-msx*" } */ +/* ICE for bit instruction generation using 16-bit const */ + +__extension__ struct st_mstp +{ + union + { + unsigned short WORD; + struct + { + unsigned char ACSE:1; + unsigned char _EXDMAC:1; + unsigned char _DMAC:1; + unsigned char _DTC:1; + unsigned char:2; + unsigned char _TMR23:1; + unsigned char _TMR01:1; + unsigned char:2; + unsigned char _DA:1; + unsigned char:1; + unsigned char _AD:1; + unsigned char:1; + unsigned char _TPUU:1; + unsigned char _TPUL:1; + } BIT; + } CRA; +}; +#define MSTP (*(volatile struct st_mstp *)0xFFFDC8) +#define MSTPA_EXDMA 0x4000 +#define MSTPA_AND 0xFEFF + +int +main () +{ + MSTP.CRA.WORD |= MSTPA_EXDMA; + MSTP.CRA.WORD ^= MSTPA_EXDMA; + MSTP.CRA.WORD &= MSTPA_AND; + return 0; +} |