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| author | Richard Henderson <rth@cygnus.com> | 1998-11-14 07:07:03 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 1998-11-14 07:07:03 -0800 |
| commit | bd8dc16507f210e0d01954e65e5d93061c560d5b (patch) | |
| tree | 026e96faa52b000fcff28e7d625148b28eab0736 /gcc | |
| parent | 9d1a7ce0ccae0ed0933a514aca56a015f45d7738 (diff) | |
| download | gcc-bd8dc16507f210e0d01954e65e5d93061c560d5b.zip gcc-bd8dc16507f210e0d01954e65e5d93061c560d5b.tar.gz gcc-bd8dc16507f210e0d01954e65e5d93061c560d5b.tar.bz2 | |
alpha.md (addsi3, subsi3): Revise 5 Nov change to store DImode value in paradoxical SImode result...
* alpha.md (addsi3, subsi3): Revise 5 Nov change to store DImode
value in paradoxical SImode result, rather than truncating midpoint.
From-SVN: r23655
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.md | 48 |
2 files changed, 32 insertions, 21 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index df3073f..4b705ff 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +Sat Nov 14 15:05:07 1998 Richard Henderson <rth@cygnus.com> + + * alpha.md (addsi3, subsi3): Revise 5 Nov change to store DImode + value in paradoxical SImode result, rather than truncating midpoint. + Fri Nov 13 22:19:23 1998 Richard Henderson <rth@cygnus.com> * alpha.c (reg_not_elim_operand): New. diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 80f2208..fde18fa 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -427,19 +427,22 @@ "" " { - rtx op1 = gen_lowpart (DImode, operands[1]); - rtx op2 = gen_lowpart (DImode, operands[2]); - - if (! cse_not_expected) + if (optimize) { - rtx tmp = gen_reg_rtx (DImode); - emit_insn (gen_adddi3 (tmp, op1, op2)); - emit_move_insn (operands[0], gen_lowpart (SImode, tmp)); + rtx op1 = gen_lowpart (DImode, operands[1]); + rtx op2 = gen_lowpart (DImode, operands[2]); + + if (! cse_not_expected) + { + rtx tmp = gen_reg_rtx (DImode); + emit_insn (gen_adddi3 (tmp, op1, op2)); + emit_move_insn (gen_lowpart (DImode, operands[0]), tmp); + } + else + emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2)); + DONE; } - else - emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2)); - DONE; -} ") +}") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") @@ -719,18 +722,21 @@ "" " { - rtx op1 = gen_lowpart (DImode, operands[1]); - rtx op2 = gen_lowpart (DImode, operands[2]); - - if (! cse_not_expected) + if (optimize) { - rtx tmp = gen_reg_rtx (DImode); - emit_insn (gen_subdi3 (tmp, op1, op2)); - emit_move_insn (operands[0], gen_lowpart (SImode, tmp)); + rtx op1 = gen_lowpart (DImode, operands[1]); + rtx op2 = gen_lowpart (DImode, operands[2]); + + if (! cse_not_expected) + { + rtx tmp = gen_reg_rtx (DImode); + emit_insn (gen_subdi3 (tmp, op1, op2)); + emit_move_insn (gen_lowpart (DImode, operands[0]), tmp); + } + else + emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2)); + DONE; } - else - emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2)); - DONE; } ") (define_insn "" |