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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-08-08 01:01:26 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-08-11 23:25:10 +0000 |
| commit | bc11cbff9e648fdda2798bfa2d7151d5cd164b87 (patch) | |
| tree | 15a332ec9b35d24ab2d376283f84f7031ce7734e /gcc | |
| parent | afd6aa80b373fdf4de6bd3ac3c5f099634ac26e2 (diff) | |
| download | gcc-bc11cbff9e648fdda2798bfa2d7151d5cd164b87.zip gcc-bc11cbff9e648fdda2798bfa2d7151d5cd164b87.tar.gz gcc-bc11cbff9e648fdda2798bfa2d7151d5cd164b87.tar.bz2 | |
aarch64: Fix condition accepted by mov<ALLI>cc
Reject QI/HImode conditions, which would require extension in
order to compare. Fixes
z.c:10:1: error: unrecognizable insn:
10 | }
| ^
(insn 23 22 24 2 (set (reg:CC 66 cc)
(compare:CC (reg:HI 128)
(reg:HI 127))) "z.c":6:6 -1
(nil))
during RTL pass: vregs
gcc:
* config/aarch64/aarch64.md (mov<ALLI>cc): Accept MODE_CC
conditions directly; reject QI/HImode conditions.
gcc/testsuite:
* gcc.target/aarch64/cmpbr-3.c: New.
* gcc.target/aarch64/ifcvt_multiple_sets_rewire.c: Simplify
test for csel by ignoring the actual registers used.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 16 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/cmpbr-3.c | 15 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_rewire.c | 4 |
3 files changed, 27 insertions, 8 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 77b4bdc..8e431a1 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4771,15 +4771,21 @@ (match_operand:ALLI 3 "register_operand")))] "" { - rtx ccreg; enum rtx_code code = GET_CODE (operands[1]); - if (code == UNEQ || code == LTGT) FAIL; - ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), - XEXP (operands[1], 1)); - operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + rtx ccreg = XEXP (operands[1], 0); + enum machine_mode ccmode = GET_MODE (ccreg); + if (GET_MODE_CLASS (ccmode) == MODE_CC) + gcc_assert (XEXP (operands[1], 1) == const0_rtx); + else if (ccmode == QImode || ccmode == HImode) + FAIL; + else + { + ccreg = aarch64_gen_compare_reg (code, ccreg, XEXP (operands[1], 1)); + operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + } } ) diff --git a/gcc/testsuite/gcc.target/aarch64/cmpbr-3.c b/gcc/testsuite/gcc.target/aarch64/cmpbr-3.c new file mode 100644 index 0000000..a4f12de --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cmpbr-3.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2" } */ + +#pragma GCC target "+cmpbr" + +long aarch64_fallback_frame_state_tpidr2_0; +unsigned short aarch64_fallback_frame_state_tpidr2_1, aarch64_fallback_frame_state_za_ctx_0; +void aarch64_fallback_frame_state_za_buffer() +{ + long num_slices = aarch64_fallback_frame_state_tpidr2_1; + if (aarch64_fallback_frame_state_tpidr2_1 > aarch64_fallback_frame_state_za_ctx_0) + num_slices = aarch64_fallback_frame_state_za_ctx_0; + __builtin_memcpy((void *)aarch64_fallback_frame_state_tpidr2_0, + aarch64_fallback_frame_state_za_buffer, num_slices); +} diff --git a/gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_rewire.c b/gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_rewire.c index 448425f..2f28756 100644 --- a/gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_rewire.c +++ b/gcc/testsuite/gcc.target/aarch64/ifcvt_multiple_sets_rewire.c @@ -14,7 +14,5 @@ void cond1(int cond, int x, int y, int z) sink2(x, y); } -/* { dg-final { scan-assembler-times "csel\tw0, w0, w1" 1 } } */ -/* { dg-final { scan-assembler-times "csel\tw1, w3, w2" 1 } } */ - +/* { dg-final { scan-assembler-times "csel" 2 } } */ /* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_convert_multiple_sets" 1 "ce1" } } */ |