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| author | Richard Earnshaw <rearnsha@arm.com> | 2012-08-17 08:50:29 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2012-08-17 08:50:29 +0000 |
| commit | b915718fdd303e6c7717749aa2a37dff0e495890 (patch) | |
| tree | ff2d0defdc46e94b1c405da9d86044ecd059f586 /gcc | |
| parent | 5deac3404d220cb68d893eb6c86ed2fa3ab3134c (diff) | |
| download | gcc-b915718fdd303e6c7717749aa2a37dff0e495890.zip gcc-b915718fdd303e6c7717749aa2a37dff0e495890.tar.gz gcc-b915718fdd303e6c7717749aa2a37dff0e495890.tar.bz2 | |
arm.md (arm_addsi3): New variant for Thumb2 16-bit ADD instruction.
* arm.md (arm_addsi3): New variant for Thumb2 16-bit ADD instruction.
* arm.c (thumb2_reorg): Don't convert an ADD instruction that's
already 16 bits.
From-SVN: r190472
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 7 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 11 |
3 files changed, 19 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ebc1002..a053f1b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2012-08-17 Richard Earnshaw <rearnsha@arm.com> + + * arm.md (arm_addsi3): New variant for Thumb2 16-bit ADD instruction. + * arm.c (thumb2_reorg): Don't convert an ADD instruction that's + already 16 bits. + 2012-08-17 Richard Guenther <rguenther@suse.de> * hash-table.h (class hash_table): Use a descriptor template diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index b799e0d..2805b7c 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -13309,6 +13309,13 @@ thumb2_reorg (void) switch (GET_CODE (src)) { case PLUS: + /* Adding two registers and storing the result + in the first source is already a 16-bit + operation. */ + if (rtx_equal_p (dst, op0) + && register_operand (op1, SImode)) + break; + if (low_register_operand (op0, SImode)) { /* ADDS <Rd>,<Rn>,<Rm> */ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index e9da56d..6a642bf 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -746,11 +746,12 @@ ;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will ;; put the duplicated register first, and not try the commutative version. (define_insn_and_split "*arm_addsi3" - [(set (match_operand:SI 0 "s_register_operand" "=r, k,r,r, k, r, k,k,r, k, r") - (plus:SI (match_operand:SI 1 "s_register_operand" "%rk,k,r,rk,k, rk,k,r,rk,k, rk") - (match_operand:SI 2 "reg_or_int_operand" "rI,rI,k,Pj,Pj,L, L,L,PJ,PJ,?n")))] + [(set (match_operand:SI 0 "s_register_operand" "=rk, r,k, r,r, k, r, k,k,r, k, r") + (plus:SI (match_operand:SI 1 "s_register_operand" "%0, rk,k, r,rk,k, rk,k,r,rk,k, rk") + (match_operand:SI 2 "reg_or_int_operand" "rk, rI,rI,k,Pj,Pj,L, L,L,PJ,PJ,?n")))] "TARGET_32BIT" "@ + add%?\\t%0, %0, %2 add%?\\t%0, %1, %2 add%?\\t%0, %1, %2 add%?\\t%0, %2, %1 @@ -773,9 +774,9 @@ operands[1], 0); DONE; " - [(set_attr "length" "4,4,4,4,4,4,4,4,4,4,16") + [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,16") (set_attr "predicable" "yes") - (set_attr "arch" "*,*,*,t2,t2,*,*,a,t2,t2,*")] + (set_attr "arch" "t2,*,*,*,t2,t2,*,*,a,t2,t2,*")] ) (define_insn_and_split "*thumb1_addsi3" |