diff options
author | Kazu Hirata <kazu@cs.umass.edu> | 2003-01-30 13:19:16 +0000 |
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committer | Kazu Hirata <kazu@gcc.gnu.org> | 2003-01-30 13:19:16 +0000 |
commit | b6d08ca1ec3de3cf5723418ddc41796d78ef5690 (patch) | |
tree | 3f6e6a023d3d6dea58de152f42dc1fd95f6c78a4 /gcc | |
parent | a693735b841b0228abc8e9eda50628d3d86381ae (diff) | |
download | gcc-b6d08ca1ec3de3cf5723418ddc41796d78ef5690.zip gcc-b6d08ca1ec3de3cf5723418ddc41796d78ef5690.tar.gz gcc-b6d08ca1ec3de3cf5723418ddc41796d78ef5690.tar.bz2 |
aix43.h: Fix comment typos.
* config/rs6000/aix43.h: Fix comment typos.
* config/rs6000/aix51.h: Likewise.
* config/rs6000/aix52.h: Likewise.
* config/rs6000/altivec.h: Likewise.
* config/rs6000/rs6000.c: Likewise.
* config/rs6000/rs6000.h: Likewise.
* config/rs6000/rs6000.md: Likewise.
* config/rs6000/spe.md: Likewise.
From-SVN: r62133
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 11 | ||||
-rw-r--r-- | gcc/config/rs6000/aix43.h | 4 | ||||
-rw-r--r-- | gcc/config/rs6000/aix51.h | 4 | ||||
-rw-r--r-- | gcc/config/rs6000/aix52.h | 4 | ||||
-rw-r--r-- | gcc/config/rs6000/altivec.h | 4 | ||||
-rw-r--r-- | gcc/config/rs6000/rs6000.c | 12 | ||||
-rw-r--r-- | gcc/config/rs6000/rs6000.h | 4 | ||||
-rw-r--r-- | gcc/config/rs6000/rs6000.md | 2 | ||||
-rw-r--r-- | gcc/config/rs6000/spe.md | 4 |
9 files changed, 30 insertions, 19 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 54129c4..9548a22 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2003-01-30 Kazu Hirata <kazu@cs.umass.edu> + + * config/rs6000/aix43.h: Fix comment typos. + * config/rs6000/aix51.h: Likewise. + * config/rs6000/aix52.h: Likewise. + * config/rs6000/altivec.h: Likewise. + * config/rs6000/rs6000.c: Likewise. + * config/rs6000/rs6000.h: Likewise. + * config/rs6000/rs6000.md: Likewise. + * config/rs6000/spe.md: Likewise. + 2003-01-29 Mark Mitchell <mark@codesourcery.com> * c-common.c (builtin_define_float_constants): Define diff --git a/gcc/config/rs6000/aix43.h b/gcc/config/rs6000/aix43.h index bcbfcf2..19cadd8 100644 --- a/gcc/config/rs6000/aix43.h +++ b/gcc/config/rs6000/aix43.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000 POWER running AIX version 4.3. - Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. Contributed by David Edelsohn (edelsohn@gnu.org). This file is part of GNU CC. @@ -62,7 +62,7 @@ do { \ #undef ASM_SPEC #define ASM_SPEC "-u %{maix64:-a64 -mppc64} %(asm_cpu)" -/* Common ASM definitions used by ASM_SPEC amonst the various targets +/* Common ASM definitions used by ASM_SPEC amongst the various targets for handling -mcpu=xxx switches. */ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ diff --git a/gcc/config/rs6000/aix51.h b/gcc/config/rs6000/aix51.h index 552394e..201b2addf 100644 --- a/gcc/config/rs6000/aix51.h +++ b/gcc/config/rs6000/aix51.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000 POWER running AIX V5. - Copyright (C) 2001 Free Software Foundation, Inc. + Copyright (C) 2001, 2003 Free Software Foundation, Inc. Contributed by David Edelsohn (edelsohn@gnu.org). This file is part of GNU CC. @@ -62,7 +62,7 @@ do { \ #undef ASM_SPEC #define ASM_SPEC "-u %{maix64:-a64 -mppc64} %(asm_cpu)" -/* Common ASM definitions used by ASM_SPEC amonst the various targets +/* Common ASM definitions used by ASM_SPEC amongst the various targets for handling -mcpu=xxx switches. */ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ diff --git a/gcc/config/rs6000/aix52.h b/gcc/config/rs6000/aix52.h index b61cc30..da7e036 100644 --- a/gcc/config/rs6000/aix52.h +++ b/gcc/config/rs6000/aix52.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000 POWER running AIX V5.2. - Copyright (C) 2002 Free Software Foundation, Inc. + Copyright (C) 2002, 2003 Free Software Foundation, Inc. Contributed by David Edelsohn (edelsohn@gnu.org). This file is part of GNU CC. @@ -62,7 +62,7 @@ do { \ #undef ASM_SPEC #define ASM_SPEC "-u %{maix64:-a64 -mppc64} %(asm_cpu)" -/* Common ASM definitions used by ASM_SPEC amonst the various targets +/* Common ASM definitions used by ASM_SPEC amongst the various targets for handling -mcpu=xxx switches. */ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index 1e2d8c8..0b789a9 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -1,5 +1,5 @@ /* PowerPC AltiVec include file. - Copyright (C) 2002 Free Software Foundation, Inc. + Copyright (C) 2002, 2003 Free Software Foundation, Inc. Contributed by Aldy Hernandez (aldyh@redhat.com). This file is part of GNU CC. @@ -41,7 +41,7 @@ Boston, MA 02111-1307, USA. */ #define __vector __attribute__((vector_size(16))) -/* You are allowed to undef this for C++ compatability. */ +/* You are allowed to undef this for C++ compatibility. */ #define vector __vector #define bool signed diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 41284e8..2d9ac48 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -4121,7 +4121,7 @@ static struct builtin_description bdesc_spe_evsel[] = { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ }, }; -/* ABS* opreations. */ +/* ABS* operations. */ static const struct builtin_description bdesc_abs[] = { @@ -5254,7 +5254,7 @@ rs6000_init_builtins () /* Search through a set of builtins and enable the mask bits. DESC is an array of builtins. - SIZE is the totaly number of builtins. + SIZE is the total number of builtins. START is the builtin enum at which to start. END is the builtin enum at which to end. */ static void @@ -6943,7 +6943,7 @@ includes_rshift_p (shiftop, andop) /* Return 1 if ANDOP is a mask suitable for use with an rldic insn to perform a left shift. It must have exactly SHIFTOP least - signifigant 0's, then one or more 1's, then zero or more 0's. */ + significant 0's, then one or more 1's, then zero or more 0's. */ int includes_rldic_lshift_p (shiftop, andop) @@ -6961,7 +6961,7 @@ includes_rldic_lshift_p (shiftop, andop) shift_mask = ~0; shift_mask <<= INTVAL (shiftop); - /* Find the least signifigant one bit. */ + /* Find the least significant one bit. */ lsb = c & -c; /* It must coincide with the LSB of the shift mask. */ @@ -8379,7 +8379,7 @@ rs6000_generate_compare (code) bit3 bit2 bit1 bit0 ... bit 2 would be a GT CR alias, so later on we - look in the GT bits for the branch instructins. + look in the GT bits for the branch instructions. However, we must be careful to emit correct RTL in the meantime, so optimizations don't get confused. */ @@ -8694,7 +8694,7 @@ rs6000_emit_cmove (dest, op, true_cond, false_cond) if (GET_CODE (op1) == CONST_DOUBLE) REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); - /* We're going to try to implement comparions by performing + /* We're going to try to implement comparisons by performing a subtract, then comparing against zero. Unfortunately, Inf - Inf is NaN which is not zero, and so if we don't know that the operand is finite and the comparison diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index b3fa442..a96984d 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -965,7 +965,7 @@ extern int rs6000_default_long_calls; we end up clobbering r11. The AltiVec case needs to be fixed. Dunno if we should break ABI - compatability and reserve a register for it as well.. */ + compatibility and reserve a register for it as well.. */ #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11) @@ -1362,7 +1362,7 @@ typedef struct rs6000_stack { enum rs6000_abi abi; /* which ABI to use */ int gp_save_offset; /* offset to save GP regs from initial SP */ int fp_save_offset; /* offset to save FP regs from initial SP */ - int altivec_save_offset; /* offset to save AltiVec regs from inital SP */ + int altivec_save_offset; /* offset to save AltiVec regs from initial SP */ int lr_save_offset; /* offset to save LR from initial SP */ int cr_save_offset; /* offset to save CR from initial SP */ int vrsave_save_offset; /* offset to save VRSAVE from initial SP */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 34415c2..6af6bee 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -6005,7 +6005,7 @@ "") ;; Twiddles bits to avoid double rounding. -;; Bits that might be trucated when converting to DFmode are replaced +;; Bits that might be truncated when converting to DFmode are replaced ;; by a bit that won't be lost at that stage, but is below the SFmode ;; rounding position. (define_expand "floatdisf2_internal2" diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md index 3413858..3b658b8 100644 --- a/gcc/config/rs6000/spe.md +++ b/gcc/config/rs6000/spe.md @@ -1,5 +1,5 @@ ;; e500 SPE description -;; Copyright (C) 2002 Free Software Foundation, Inc. +;; Copyright (C) 2002, 2003 Free Software Foundation, Inc. ;; Contributed by Aldy Hernandez (aldy@quesejoda.com) ;; This file is part of GNU CC. @@ -736,7 +736,7 @@ ;; SPE SIMD load instructions. -;; Only the hardware engineer who designed the SPE inderstands the +;; Only the hardware engineer who designed the SPE understands the ;; plethora of load and store instructions ;-). We have no way of ;; differentiating between them with RTL so use an unspec of const_int 0 ;; to avoid identical RTL. |