diff options
author | Haochen Jiang <haochen.jiang@intel.com> | 2023-10-09 16:09:57 +0800 |
---|---|---|
committer | Haochen Jiang <haochen.jiang@intel.com> | 2023-10-09 17:08:40 +0800 |
commit | b54900552aae8226b5ea225e472279c1023b1879 (patch) | |
tree | d88a45e3f8c3796859073776520cdc2a5691bd2d /gcc | |
parent | 8e79b1b45a4d74aa866de5abc7bf3ef68e617f06 (diff) | |
download | gcc-b54900552aae8226b5ea225e472279c1023b1879.zip gcc-b54900552aae8226b5ea225e472279c1023b1879.tar.gz gcc-b54900552aae8226b5ea225e472279c1023b1879.tar.bz2 |
Support -mevex512 for AVX512{IFMA,VBMI,VNNI,BF16,VPOPCNTDQ,VBMI2,BITALG,VP2INTERSECT},VAES,GFNI,VPCLMULQDQ intrins
gcc/ChangeLog:
* config/i386/sse.md (VI1_AVX512VL): Add TARGET_EVEX512.
(VI8_FVL): Ditto.
(VI1_AVX512F): Ditto.
(VI1_AVX512VNNI): Ditto.
(VI1_AVX512VL_F): Ditto.
(VI12_VI48F_AVX512VL): Ditto.
(*avx512f_permvar_truncv32hiv32qi_1): Ditto.
(sdot_prod<mode>): Ditto.
(VEC_PERM_AVX2): Ditto.
(VPERMI2): Ditto.
(VPERMI2I): Ditto.
(vpmadd52<vpmadd52type>v8di): Ditto.
(usdot_prod<mode>): Ditto.
(vpdpbusd_v16si): Ditto.
(vpdpbusds_v16si): Ditto.
(vpdpwssd_v16si): Ditto.
(vpdpwssds_v16si): Ditto.
(VI48_AVX512VP2VL): Ditto.
(avx512vp2intersect_2intersectv16si): Ditto.
(VF_AVX512BF16VL): Ditto.
(VF1_AVX512_256): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr90096.c: Adjust error message.
Co-authored-by: Hu, Lin1 <lin1.hu@intel.com>
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/config/i386/sse.md | 56 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/pr90096.c | 2 |
2 files changed, 31 insertions, 27 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 40cf913..e776189 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -298,7 +298,7 @@ (V32BF "TARGET_EVEX512") (V16BF "TARGET_AVX512VL") (V8BF "TARGET_AVX512VL")]) (define_mode_iterator VI1_AVX512VL - [V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL")]) + [(V64QI "TARGET_EVEX512") (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL")]) ;; All vector modes (define_mode_iterator V @@ -531,7 +531,7 @@ [(V8DI "TARGET_AVX512F && TARGET_EVEX512") (V4DI "TARGET_AVX") V2DI]) (define_mode_iterator VI8_FVL - [(V8DI "TARGET_AVX512F") V4DI (V2DI "TARGET_AVX512VL")]) + [(V8DI "TARGET_AVX512F && TARGET_EVEX512") V4DI (V2DI "TARGET_AVX512VL")]) (define_mode_iterator VI8_AVX512VL [(V8DI "TARGET_EVEX512") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) @@ -546,10 +546,10 @@ [(V64QI "TARGET_AVX512BW && TARGET_EVEX512") (V32QI "TARGET_AVX2") V16QI]) (define_mode_iterator VI1_AVX512F - [(V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI]) + [(V64QI "TARGET_AVX512F && TARGET_EVEX512") (V32QI "TARGET_AVX") V16QI]) (define_mode_iterator VI1_AVX512VNNI - [(V64QI "TARGET_AVX512VNNI") (V32QI "TARGET_AVX2") V16QI]) + [(V64QI "TARGET_AVX512VNNI && TARGET_EVEX512") (V32QI "TARGET_AVX2") V16QI]) (define_mode_iterator VI12_256_512_AVX512VL [(V64QI "TARGET_EVEX512") (V32QI "TARGET_AVX512VL") @@ -599,7 +599,7 @@ V8DI ]) (define_mode_iterator VI1_AVX512VL_F - [V32QI (V16QI "TARGET_AVX512VL") (V64QI "TARGET_AVX512F")]) + [V32QI (V16QI "TARGET_AVX512VL") (V64QI "TARGET_AVX512F && TARGET_EVEX512")]) (define_mode_iterator VI8_AVX2_AVX512BW [(V8DI "TARGET_AVX512BW && TARGET_EVEX512") (V4DI "TARGET_AVX2") V2DI]) @@ -923,8 +923,8 @@ (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL") - V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL") - V32HI (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")]) + (V64QI "TARGET_EVEX512") (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL") + (V32HI "TARGET_EVEX512") (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")]) (define_mode_iterator VI48F_256 [V8SI V8SF V4DI V4DF]) @@ -14262,7 +14262,7 @@ (const_int 26) (const_int 27) (const_int 28) (const_int 29) (const_int 30) (const_int 31)])))] - "TARGET_AVX512VBMI && ix86_pre_reload_split ()" + "TARGET_AVX512VBMI && TARGET_EVEX512 && ix86_pre_reload_split ()" "#" "&& 1" [(set (match_dup 0) @@ -16087,7 +16087,7 @@ "TARGET_SSE2" { /* Try with vnni instructions. */ - if ((<MODE_SIZE> == 64 && TARGET_AVX512VNNI) + if ((<MODE_SIZE> == 64 && TARGET_AVX512VNNI && TARGET_EVEX512) || (<MODE_SIZE> < 64 && ((TARGET_AVX512VNNI && TARGET_AVX512VL) || TARGET_AVXVNNI))) { @@ -17377,7 +17377,8 @@ (V8DF "TARGET_AVX512F && TARGET_EVEX512") (V16SI "TARGET_AVX512F && TARGET_EVEX512") (V8DI "TARGET_AVX512F && TARGET_EVEX512") - (V32HI "TARGET_AVX512BW && TARGET_EVEX512") (V64QI "TARGET_AVX512VBMI") + (V32HI "TARGET_AVX512BW && TARGET_EVEX512") + (V64QI "TARGET_AVX512VBMI && TARGET_EVEX512") (V32HF "TARGET_AVX512FP16")]) (define_expand "vec_perm<mode>" @@ -27186,7 +27187,8 @@ (V32HI "TARGET_AVX512BW && TARGET_EVEX512") (V16HI "TARGET_AVX512BW && TARGET_AVX512VL") (V8HI "TARGET_AVX512BW && TARGET_AVX512VL") - (V64QI "TARGET_AVX512VBMI") (V32QI "TARGET_AVX512VBMI && TARGET_AVX512VL") + (V64QI "TARGET_AVX512VBMI && TARGET_EVEX512") + (V32QI "TARGET_AVX512VBMI && TARGET_AVX512VL") (V16QI "TARGET_AVX512VBMI && TARGET_AVX512VL")]) (define_mode_iterator VPERMI2I @@ -27196,7 +27198,8 @@ (V32HI "TARGET_AVX512BW && TARGET_EVEX512") (V16HI "TARGET_AVX512BW && TARGET_AVX512VL") (V8HI "TARGET_AVX512BW && TARGET_AVX512VL") - (V64QI "TARGET_AVX512VBMI") (V32QI "TARGET_AVX512VBMI && TARGET_AVX512VL") + (V64QI "TARGET_AVX512VBMI && TARGET_EVEX512") + (V32QI "TARGET_AVX512VBMI && TARGET_AVX512VL") (V16QI "TARGET_AVX512VBMI && TARGET_AVX512VL")]) (define_expand "<avx512>_vpermi2var<mode>3_mask" @@ -29212,7 +29215,7 @@ (match_operand:V8DI 2 "register_operand" "v") (match_operand:V8DI 3 "nonimmediate_operand" "vm")] VPMADD52))] - "TARGET_AVX512IFMA" + "TARGET_AVX512IFMA && TARGET_EVEX512" "vpmadd52<vpmadd52type>\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "ssemuladd") (set_attr "prefix" "evex") @@ -29817,9 +29820,9 @@ (match_operand:VI1_AVX512VNNI 1 "register_operand") (match_operand:VI1_AVX512VNNI 2 "register_operand") (match_operand:<ssedvecmode> 3 "register_operand")] - "(<MODE_SIZE> == 64 - ||((TARGET_AVX512VNNI && TARGET_AVX512VL) - || TARGET_AVXVNNI))" + "((<MODE_SIZE> == 64 && TARGET_EVEX512) + || ((TARGET_AVX512VNNI && TARGET_AVX512VL) + || TARGET_AVXVNNI))" { operands[1] = lowpart_subreg (<ssedvecmode>mode, force_reg (<MODE>mode, operands[1]), @@ -29840,7 +29843,7 @@ (match_operand:V16SI 2 "register_operand" "v") (match_operand:V16SI 3 "nonimmediate_operand" "vm")] UNSPEC_VPDPBUSD))] - "TARGET_AVX512VNNI" + "TARGET_AVX512VNNI && TARGET_EVEX512" "vpdpbusd\t{%3, %2, %0|%0, %2, %3}" [(set_attr ("prefix") ("evex"))]) @@ -29908,7 +29911,7 @@ (match_operand:V16SI 2 "register_operand" "v") (match_operand:V16SI 3 "nonimmediate_operand" "vm")] UNSPEC_VPDPBUSDS))] - "TARGET_AVX512VNNI" + "TARGET_AVX512VNNI && TARGET_EVEX512" "vpdpbusds\t{%3, %2, %0|%0, %2, %3}" [(set_attr ("prefix") ("evex"))]) @@ -29976,7 +29979,7 @@ (match_operand:V16SI 2 "register_operand" "v") (match_operand:V16SI 3 "nonimmediate_operand" "vm")] UNSPEC_VPDPWSSD))] - "TARGET_AVX512VNNI" + "TARGET_AVX512VNNI && TARGET_EVEX512" "vpdpwssd\t{%3, %2, %0|%0, %2, %3}" [(set_attr ("prefix") ("evex"))]) @@ -30044,7 +30047,7 @@ (match_operand:V16SI 2 "register_operand" "v") (match_operand:V16SI 3 "nonimmediate_operand" "vm")] UNSPEC_VPDPWSSDS))] - "TARGET_AVX512VNNI" + "TARGET_AVX512VNNI && TARGET_EVEX512" "vpdpwssds\t{%3, %2, %0|%0, %2, %3}" [(set_attr ("prefix") ("evex"))]) @@ -30167,9 +30170,9 @@ (set_attr "mode" "<sseinsnmode>")]) (define_mode_iterator VI48_AVX512VP2VL - [V8DI - (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") - (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")]) + [(V8DI "TARGET_EVEX512") + (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") + (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")]) (define_mode_iterator MASK_DWI [P2QI P2HI]) @@ -30210,12 +30213,12 @@ (unspec:P2HI [(match_operand:V16SI 1 "register_operand" "v") (match_operand:V16SI 2 "vector_operand" "vm")] UNSPEC_VP2INTERSECT))] - "TARGET_AVX512VP2INTERSECT" + "TARGET_AVX512VP2INTERSECT && TARGET_EVEX512" "vp2intersectd\t{%2, %1, %0|%0, %1, %2}" [(set_attr ("prefix") ("evex"))]) (define_mode_iterator VF_AVX512BF16VL - [V32BF (V16BF "TARGET_AVX512VL") (V8BF "TARGET_AVX512VL")]) + [(V32BF "TARGET_EVEX512") (V16BF "TARGET_AVX512VL") (V8BF "TARGET_AVX512VL")]) ;; Converting from BF to SF (define_mode_attr bf16_cvt_2sf [(V32BF "V16SF") (V16BF "V8SF") (V8BF "V4SF")]) @@ -30308,7 +30311,8 @@ "TARGET_AVX512BF16 && TARGET_AVX512VL" "vcvtneps2bf16{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}") -(define_mode_iterator VF1_AVX512_256 [V16SF (V8SF "TARGET_AVX512VL")]) +(define_mode_iterator VF1_AVX512_256 + [(V16SF "TARGET_EVEX512") (V8SF "TARGET_AVX512VL")]) (define_expand "avx512f_cvtneps2bf16_<mode>_maskz" [(match_operand:<sf_cvt_bf16> 0 "register_operand") diff --git a/gcc/testsuite/gcc.target/i386/pr90096.c b/gcc/testsuite/gcc.target/i386/pr90096.c index 871e0ff..74f052e 100644 --- a/gcc/testsuite/gcc.target/i386/pr90096.c +++ b/gcc/testsuite/gcc.target/i386/pr90096.c @@ -10,7 +10,7 @@ volatile __mmask64 m64; void foo (int i) { - x1 = _mm512_gf2p8affineinv_epi64_epi8 (x1, x2, 3); /* { dg-error "needs isa option -mgfni -mavx512f" } */ + x1 = _mm512_gf2p8affineinv_epi64_epi8 (x1, x2, 3); /* { dg-error "needs isa option -mevex512 -mgfni -mavx512f" } */ } #ifdef __x86_64__ |