Replacement file, for as1750.

From-SVN: r8109

2 files changed, 581 insertions, 505 deletions

diff --git a/gcc/config/1750a/1750a.c b/gcc/config/1750a/1750a.c
index 67cf864..d2a117b 100644
--- a/gcc/config/1750a/1750a.c
+++ b/gcc/config/1750a/1750a.c
@@ -1,6 +1,6 @@
-/* Subroutines for insn-output.c for MIL-STD-1750A.
+/* Subroutines for insn-output.c for MIL-STD-1750.
    Copyright (C) 1994 Free Software Foundation, Inc.
-   Contributed by O.M.Kellogg, Deutsche Aerospace (okellogg@salyko.cube.net).
+   Contributed by O.M.Kellogg, DASA (okellogg@salyko.cube.net).
 
 This file is part of GNU CC.
 
@@ -36,11 +36,13 @@ int datalbl_ndx = -1;
 struct jumplabel_array jmplbl[JMPLBL_ARRSIZ];
 int jmplbl_ndx = -1;
 int label_pending = 0, program_counter = 0;
-enum section  current_section=NREL;
-char *sectname[4] = { "NREL","IREL","KREL","SREL" };
+enum section current_section = Normal;
+char *sectname[4] =
+{"Normal", "Init", "Konst", "Static"};
 
-int notice_update_cc(exp)
-  rtx exp;
+int
+notice_update_cc (exp)
+     rtx exp;
 {
   if (GET_CODE (exp) == SET)
     {
@@ -66,8 +68,8 @@ int notice_update_cc(exp)
 	}
       /* Emulated longword bit-ops leave cc's incorrect */
       else if (GET_MODE (SET_DEST (exp)) == HImode ?
-               src_code == AND || src_code == IOR ||
-               src_code == XOR || src_code == NOT : 0)
+	       src_code == AND || src_code == IOR ||
+	       src_code == XOR || src_code == NOT : 0)
 	{
 	  CC_STATUS_INIT;
 	  return;
@@ -82,7 +84,7 @@ int notice_update_cc(exp)
       /* Anything that lands in a reg will set cc_status. */
       else if (REG_P (SET_DEST (exp)))
 	{
-          cc_status.flags = CC_NO_OVERFLOW;
+	  cc_status.flags = CC_NO_OVERFLOW;
 	  cc_status.value1 = SET_SRC (exp);
 	  cc_status.value2 = SET_DEST (exp);
 	  return;
@@ -112,116 +114,119 @@ int notice_update_cc(exp)
 }
 
 
-rtx function_arg(cum,mode,type,named)
-  int cum;
-  enum machine_mode mode;
-  tree type;
-  int named;
+rtx
+function_arg (cum, mode, type, named)
+     int cum;
+     enum machine_mode mode;
+     tree type;
+     int named;
 {
   int size;
   rtx result;
 
-  if (MUST_PASS_IN_STACK(mode,type))
+  if (MUST_PASS_IN_STACK (mode, type))
     return (rtx) 0;
   if (mode == BLKmode)
-    size = int_size_in_bytes(type);
+    size = int_size_in_bytes (type);
   else
     size = GET_MODE_SIZE (mode);
-  if (cum + size < 12) 
-    return gen_rtx(REG, mode, cum);
+  if (cum + size < 12)
+    return gen_rtx (REG, mode, cum);
   else
     return (rtx) 0;
 }
 
 
-char *tekasm_float(exp_char,value)
-  char exp_char;
-  double value;
+#ifndef STRDUP
+char *
+strdup (str)
+     char *str;
 {
-  extern char *strpbrk();
-  int found_letter = 0;
   char *p;
-  static char fbuf[20];
-    
-  sprintf(fbuf,"%g",value);
-  if ((p = strpbrk(fbuf,"Ee")) == NULL)
-    sprintf(fbuf+strlen(fbuf),"%c0",exp_char);
-  else
-    *p = exp_char;
-  return fbuf;
+  if (str == NULL)
+    return NULL;
+  if ((p = (char *) malloc (strlen (str) + 1)) == NULL)
+    {
+      fprintf (stderr, "dynamic memory exhausted");
+      abort ();
+    }
+  return strcpy (p, str);
 }
 
-char *asm_float_syntax(rtx x)
+#endif
+
+
+double
+get_double (x)
+     rtx x;
 {
-  if (GET_MODE(x) == HFmode)
+  union
     {
-      union { double d; int i[2]; } du;
-      union { float f; int i; } su;
-      du.i[0] = CONST_DOUBLE_LOW(x);
-      du.i[1] = CONST_DOUBLE_HIGH(x);
-      su.f = (float) du.d;
-      return tekasm_float('E',su.f);
-    }
-  else
-    {
-      union { double d; int i[2]; } du;
-      du.i[0] = CONST_DOUBLE_LOW(x);
-      du.i[1] = CONST_DOUBLE_HIGH(x);
-      return tekasm_float('D',du.d);
+      double d;
+      long i[2];
     }
+  du;
+
+  du.i[0] = CONST_DOUBLE_LOW (x);
+  du.i[1] = CONST_DOUBLE_HIGH (x);
+  return du.d;
 }
 
-char *float_label(char code,char *fltstr)
+char *
+float_label (code, value)
+     char code;
+     double value;
 {
-    int i=1;
-    static char label[32];
-    
-    label[0] = code;
-    while (*fltstr)
+  int i = 1;
+  static char label[32];
+  char *p;
+
+  label[0] = code;
+  p = label + 1;
+  sprintf (p, "%lf", value);
+  while (*p)
     {
-	label[i] = (*fltstr == '+') ? 'p' :
-		   (*fltstr == '-') ? 'm' : *fltstr;
-	i++;
-	fltstr++;
+      *p = (*p == '+') ? 'p' :
+	(*p == '-') ? 'm' : *p;
+      p++;
     }
-    if (i > 11)
-	i = 11;
-    label[i] = '\0';
-    return label;
+  return strdup (label);
 }
 
 
-char *movcnt_regno_adjust(rtx *op)
+char *
+movcnt_regno_adjust (rtx * op)
 {
   static char outstr[40];
-  int cntreg = REGNO(op[2]), cntreg_1750 = REGNO(op[0]) + 1;
-  int dstreg = REGNO(op[0]), srcreg = REGNO(op[1]);
+  int cntreg = REGNO (op[2]), cntreg_1750 = REGNO (op[0]) + 1;
+  int dstreg = REGNO (op[0]), srcreg = REGNO (op[1]);
 
   if (cntreg == cntreg_1750)
-    sprintf(outstr,"MOV    R%%0,R%%1");
-  else if (dstreg+1 == srcreg && srcreg == cntreg+2)
-    sprintf(outstr,"XWR    R%d,R%d\n\tMOV    R%%0,R%%1",cntreg,dstreg);
-  else if (dstreg+1 == srcreg && srcreg < cntreg)
-    sprintf(outstr,"XWR    R%d,R%d\n\tMOV    R%%0,R%%1",srcreg,cntreg);
-  else if (srcreg+1 == cntreg && dstreg > cntreg)
-    sprintf(outstr,"XWR    R%d,R%d\n\tMOV    R%%0,R%%1",srcreg,dstreg);
+    sprintf (outstr, "mov r%%0,r%%1");
+  else if (dstreg + 1 == srcreg && srcreg == cntreg + 2)
+    sprintf (outstr, "xwr r%d,r%d\n\tmov r%%0,r%%1", cntreg, dstreg);
+  else if (dstreg + 1 == srcreg && srcreg < cntreg)
+    sprintf (outstr, "xwr r%d,r%d\n\tmov r%%0,r%%1", srcreg, cntreg);
+  else if (srcreg + 1 == cntreg && dstreg > cntreg)
+    sprintf (outstr, "xwr r%d,r%d\n\tmov r%%0,r%%1", srcreg, dstreg);
   else
-    sprintf(outstr,"XWR    R%d,R%d\n\tMOV    R%%0,%%1\n\tXWR     R%d,R%d",
-		   cntreg,cntreg_1750,cntreg_1750,cntreg);
+    sprintf (outstr, "xwr r%d,r%d\n\tmov r%%0,%%1\n\txwr r%d,r%d",
+	     cntreg, cntreg_1750, cntreg_1750, cntreg);
   return outstr;
 }
 
-char *mod_regno_adjust(char *instr,rtx *op)
+char *
+mod_regno_adjust (char *instr, rtx * op)
 {
   static char outstr[40];
-  char *r = (!strncmp(instr,"DVR",3) ? "R" : "");
-  int modregno_gcc = REGNO(op[3]), modregno_1750 = REGNO(op[0]) + 1;
+  char *r = (!strncmp (instr, "dvr", 3) ? "r" : "");
+  int modregno_gcc = REGNO (op[3]), modregno_1750 = REGNO (op[0]) + 1;
 
   if (modregno_gcc == modregno_1750)
-    sprintf(outstr,"%s   R%%0,%s%%2",instr,r);
+    sprintf (outstr, "%s r%%0,%s%%2", instr, r);
   else
-    sprintf(outstr,"LR     R%d,R%d\n\t%s   R%%0,%s%%2\n\tXWR     R%d,R%d",
-	    modregno_gcc,modregno_1750,instr,r,modregno_1750,modregno_gcc);
+    sprintf (outstr, "lr r%d,r%d\n\t%s r%%0,%s%%2\n\txwr r%d,r%d",
+	modregno_gcc, modregno_1750, instr, r, modregno_1750, modregno_gcc);
   return outstr;
 }
 
@@ -229,59 +234,62 @@ char *mod_regno_adjust(char *instr,rtx *op)
 /* Auxiliary to `nonindirect_operand':
    Check if op is a valid memory operand for 1750A arith./logic (non-move)
    instructions. */
-int memop_valid(register rtx op)
+int
+memop_valid (register rtx op)
 {
-  if (GET_MODE(op) != Pmode && GET_MODE(op) != VOIDmode)
+  if (GET_MODE (op) != Pmode && GET_MODE (op) != VOIDmode)
     return 0;
-  switch (GET_CODE(op))
+  switch (GET_CODE (op))
     {
-      case MEM:
-      case MINUS:
-      case MULT:
-      case DIV:
-	return 0;
-      case PLUS:
-	if (! memop_valid(XEXP(op,0)))
-	    return 0;
-	return memop_valid(XEXP(op,1));
-      case REG:
-	if (REGNO(op) > 0)
-	    return 1;
+    case MEM:
+    case MINUS:
+    case MULT:
+    case DIV:
+      return 0;
+    case PLUS:
+      if (!memop_valid (XEXP (op, 0)))
 	return 0;
-      case CONST:
-      case CONST_INT:
-      case SYMBOL_REF:
-      case SUBREG:
-	return 1;
-      default:
-	printf("memop_valid: code=%d\n",(int) GET_CODE(op));
+      return memop_valid (XEXP (op, 1));
+    case REG:
+      if (REGNO (op) > 0)
 	return 1;
+      return 0;
+    case CONST:
+    case CONST_INT:
+    case SYMBOL_REF:
+    case SUBREG:
+      return 1;
+    default:
+      printf ("memop_valid: code=%d\n", (int) GET_CODE (op));
+      return 1;
     }
 }
 
 /* extra predicate for recog: */
-int nonindirect_operand(register rtx op, enum machine_mode mode)
+int
+nonindirect_operand (register rtx op, enum machine_mode mode)
 {
   int retval;
 
-  switch (GET_CODE(op))
+  switch (GET_CODE (op))
     {
-      case MEM:
-	retval = memop_valid(XEXP(op,0));
-	return retval;
-      case REG:
-	return 1;
-      default:
-	if (! CONSTANT_P(op))
-	    return 0;
+    case MEM:
+      retval = memop_valid (XEXP (op, 0));
+      return retval;
+    case REG:
+      return 1;
+    default:
+      if (!CONSTANT_P (op))
+	return 0;
     }
   return 1;
 }
 
 /* predicate for the STC instruction: */
-int small_nonneg_const(register rtx op, enum machine_mode mode)
+int
+small_nonneg_const (register rtx op, enum machine_mode mode)
 {
-  if (GET_CODE(op) == CONST_INT && INTVAL(op) >= 0 && INTVAL(op) <= 15)
+  if (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) <= 15)
     return 1;
   return 0;
 }
@@ -289,7 +297,8 @@ int small_nonneg_const(register rtx op, enum machine_mode mode)
 /* Decide whether to output a conditional jump as a "Jump Conditional"
    or as a "Branch Conditional": */
 
-int find_jmplbl(int labelnum)
+int
+find_jmplbl (int labelnum)
 {
   int i, found = 0;
 
@@ -304,227 +313,276 @@ int find_jmplbl(int labelnum)
   return -1;
 }
 
-char *branch_or_jump(char *condition, int targetlabel_number)
+char *
+branch_or_jump (char *condition, int targetlabel_number)
 {
   static char buf[30];
   int index;
 
-  if ((index = find_jmplbl(targetlabel_number)) >= 0)
+  if ((index = find_jmplbl (targetlabel_number)) >= 0)
     if (program_counter - jmplbl[index].pc < 128)
       {
-	sprintf(buf,"B%s    %%l0",condition);
+	sprintf (buf, "b%s %%l0", condition);
 	return buf;
       }
-  sprintf(buf,"JC     %s,%%l0",condition);
+  sprintf (buf, "jc %s,%%l0", condition);
   return buf;
 }
 
 
 
-/* The PRINT_OPERAND and PRINT_OPERAND_ADDRESS macros have been 
+/* The PRINT_OPERAND and PRINT_OPERAND_ADDRESS macros have been
    made functions: */
 
-print_operand(file, x, code)
-  FILE *file;
-  rtx x;
-  enum rtx_code code;
-{ 
-  switch (GET_CODE(x))
+print_operand (file, x, kode)
+     FILE *file;
+     rtx x;
+     enum rtx_code kode;
+{
+  switch (GET_CODE (x))
     {
-      case REG:
-        fprintf (file, "%d",REGNO (x));
-        break;
-      case SYMBOL_REF:
-        fprintf(file,"%s",XSTR(x,0));
-        break;
-      case LABEL_REF:
-      case CONST:
-      case MEM:
-        output_address(XEXP(x,0));
-        break;
-      case CONST_DOUBLE:
-        if (code == 'D' || code == 'E')	/* KREL output hack: */
-          {		/* make a label out of a floating-point number. */
-            char *fltstr = (char *)asm_float_syntax(x);
-            int i, found = 0;
-            for (i = 0; i <= datalbl_ndx; i++)
-	      if (strcmp(fltstr,datalbl[i].value) == 0) { found = 1; break; }
-            if (! found)
+    case REG:
+      fprintf (file, "%d", REGNO (x));
+      break;
+    case SYMBOL_REF:
+      fprintf (file, "%s", XSTR (x, 0));
+      break;
+    case LABEL_REF:
+    case CONST:
+    case MEM:
+      output_address (XEXP (x, 0));
+      break;
+    case CONST_DOUBLE:
+/*    {
+	double value = get_double (x);
+	char fltstr[32];
+	sprintf (fltstr, "%lf", value);
+
+	if (kode == 'D' || kode == 'E')
+	  {
+	    int i, found = 0;
+	    for (i = 0; i <= datalbl_ndx; i++)
+	      if (strcmp (fltstr, datalbl[i].value) == 0)
+		{
+		  found = 1;
+		  break;
+		}
+	    if (!found)
 	      {
-	        strcpy(datalbl[i = ++datalbl_ndx].value,fltstr);
-                strcpy(datalbl[i].name,(char *)float_label(code,fltstr));
-	        datalbl[i].size = (code=='D') ? 3 : 2;
-	        check_section(KREL);
-	        fprintf(file,"K%s \tDATAF %s ;p_o\n", datalbl[i].name,fltstr);
-	        check_section(NREL);
-              }
-          }
-	else if (code == 'F')
+		strcpy (datalbl[i = ++datalbl_ndx].value, fltstr);
+		datalbl[i].name = float_label (kode, value);
+		datalbl[i].size = (kode == 'E') ? 3 : 2;
+		check_section (Konst);
+		fprintf (file, "K%s \tdata%s %s ;p_o\n", datalbl[i].name,
+			(kode == 'E' ? "ef" : "f"), fltstr);
+		check_section (Normal);
+	      }
+	  }
+	else if (kode == 'F' || kode == 'G')
 	  {
-            char *fltstr = (char *)asm_float_syntax(x);
-            int i, found = 0;
-            for (i = 0; i <= datalbl_ndx; i++)
-	      if (strcmp(fltstr,datalbl[i].value) == 0)
+	    int i, found = 0;
+	    for (i = 0; i <= datalbl_ndx; i++)
+	      if (strcmp (fltstr, datalbl[i].value) == 0)
 		{
 		  found = 1;
 		  break;
 		}
-            if (! found)
+	    if (!found)
 	      {
-		printf("Aborting: 'F' float label not found in datalbl[].\n");
-	 	abort();
+		fprintf (stderr,
+		   "float value %lfnot found upon label reference\n", value);
+		strcpy (datalbl[i = ++datalbl_ndx].value, fltstr);
+		datalbl[i].name = float_label (kode, value);
+		datalbl[i].size = (kode == 'G') ? 3 : 2;
+		check_section (Konst);
+		fprintf (file, "K%s \tdata%s %s ;p_o\n", datalbl[i].name,
+			(kode == 'G' ? "ef" : "f"), fltstr);
+		check_section (Normal);
 	      }
-	    fprintf(file,"%s ;P_O 'F'",datalbl[i].name);
-          }
+	    fprintf (file, "%s ;P_O 'F'", datalbl[i].name);
+	  }
 	else
-	  fprintf(file,"%s  ;P_O cst_dbl",(char *)asm_float_syntax(x));
-	break;
-      case CONST_INT:
-	if (code == 'J')
-	  fprintf (file, "%d",-INTVAL(x));
-	else if (INTVAL(x) > 0x7FFF)
-	  fprintf (file, "%d  ; range correction (val>0x7FFF) applied",
-	 		 INTVAL(x) - 0x10000);
+	  fprintf (file, " %s  ;P_O cst_dbl ", fltstr);
+      }
+ */
+      fprintf (file, "%lf", get_double (x));
+      break;
+    case CONST_INT:
+      if (kode == 'J')
+	fprintf (file, "%d", -INTVAL (x));
+      else if (INTVAL (x) > 0x7FFF)
+	fprintf (file, "%d  ; range correction (val>0x7FFF) applied",
+		 INTVAL (x) - 0x10000);
+      else
+	fprintf (file, "%d", INTVAL (x));
+      break;
+    case CODE_LABEL:
+      fprintf (file, "L%d", XINT (x, 3));
+      break;
+    case CALL:
+      fprintf (file, "CALL nargs=%d, func is either '%s' or '%s'",
+       XEXP (x, 1), XSTR (XEXP (XEXP (x, 0), 1), 0), XSTR (XEXP (x, 0), 1));
+      break;
+    case PLUS:
+      {
+	rtx op0 = XEXP (x, 0), op1 = XEXP (x, 1);
+	int op0code = GET_CODE (op0), op1code = GET_CODE (op1);
+	if (op1code == CONST_INT)
+	  switch (op0code)
+	    {
+	    case REG:
+	      fprintf (file, "%d,r%d  ; p_o_PLUS for REG and CONST",
+		       INTVAL (op1), REGNO (op0));
+	      break;
+	    case SYMBOL_REF:
+	      fprintf (file, "%d+%s", INTVAL (op1), XSTR (op0, 0));
+	      break;
+	    case MEM:
+	      fprintf (file, "%d,[mem:", INTVAL (op1));
+	      output_address (XEXP (op0, 0));
+	      fprintf (file, "] ;P_O plus");
+	      break;
+	    default:
+	      fprintf (file, "p_o_PLUS UFO, code=%d, with CONST=%d",
+		       (int) op0code, INTVAL (op1));
+	    }
+	else if (op1code == SYMBOL_REF && op0code == REG)
+	  fprintf (file, "%s,r%d  ; P_O: (plus reg sym)",
+		   XSTR (op1, 0), REGNO (op0));
 	else
-	  fprintf (file, "%d", INTVAL(x));
-	break;
-      case CODE_LABEL:
-	fprintf (file, "L%d", XINT(x,3));
-	break;
-      case CALL:
-	fprintf(file,"CALL nargs=%d, func is either '%s' or '%s'",
-                XEXP(x,1),XSTR(XEXP(XEXP(x,0),1),0),XSTR(XEXP(x,0),1));
-	break;
-      case PLUS:
-        {
-	  rtx op0 = XEXP(x,0), op1 = XEXP(x,1);
-	  int op0code=GET_CODE(op0), op1code=GET_CODE(op1);
-          if (op1code == CONST_INT)
-            switch (op0code)
-	      {
-		case REG:
-		  fprintf(file,"%d,R%d  ; p_o_PLUS for REG and CONST",
-			INTVAL(op1),REGNO(op0));
-		  break;
-		case SYMBOL_REF:
-		  fprintf(file,"%d+%s",INTVAL(op1),XSTR(op0,0));
-		  break;
-		case MEM:
-		  fprintf(file,"%d,[mem:",INTVAL(op1));
-		  output_address(XEXP(op0,0));
-		  fprintf(file,"] ;P_O plus");
-		  break;
-		default:
-		  fprintf(file,"p_o_PLUS UFO, code=%d, with CONST=%d",
-				(int)op0code,INTVAL(op1));
-	      }
-	  else if (op1code == SYMBOL_REF && op0code == REG)
-	    fprintf(file,"%s,R%d  ; P_O: (plus reg sym)",
-			XSTR(op1,0),REGNO(op0));
-          else
-            fprintf(file,"p_o_+: op0code=%d, op1code=%d",op0code,op1code);
-        }
-	break;
-      default:
-	fprintf (file, "p_o_UFO code=%d", GET_CODE(x));
+	  fprintf (file, "p_o_+: op0code=%d, op1code=%d", op0code, op1code);
+      }
+      break;
+    default:
+      fprintf (file, "p_o_UFO code=%d", GET_CODE (x));
     }
 }
 
-print_operand_address(file, addr)
-  FILE *file;
-  rtx addr;
+print_operand_address (file, addr)
+     FILE *file;
+     rtx addr;
 {
   switch (GET_CODE (addr))
     {
-      case REG:
-	fprintf (file, "0,R%d ; P_O_A", REGNO (addr));
-	break;
-      case PLUS:
-	{
-	  register rtx x = XEXP(addr,0), y = XEXP(addr,1);
-	  switch (GET_CODE(x))
-	    {
-	      case REG:
-                switch (GET_CODE(y))
-		  {
-		    case CONST:
-		      output_address(XEXP(y,0));
-		      fprintf(file, ",R%d ;P_O_A reg + const expr",REGNO(x));
-		      break;
-		    case CONST_INT:
-		      fprintf(file,"%d,R%d  ; P_O_A reg + const_int",
-				INTVAL(y),REGNO(x));
-		      break;
-		    case SYMBOL_REF:
-		      fprintf(file,"%s,R%d  ; P_O_A reg + sym",
-				XSTR(y,0),REGNO(x));
-		      break;
-		    default:
-		      fprintf(file, "[P_O_A reg%d+UFO code=%d]",
-			        REGNO(x),GET_CODE(y));
-	 	  }
+    case REG:
+      fprintf (file, "0,r%d ; P_O_A", REGNO (addr));
+      break;
+    case PLUS:
+      {
+	register rtx x = XEXP (addr, 0), y = XEXP (addr, 1);
+	switch (GET_CODE (x))
+	  {
+	  case REG:
+	    switch (GET_CODE (y))
+	      {
+	      case CONST:
+		output_address (XEXP (y, 0));
+		fprintf (file, ",r%d ;P_O_A reg + const expr", REGNO (x));
+		break;
+	      case CONST_INT:
+		fprintf (file, "%d,r%d", INTVAL (y), REGNO (x));
 		break;
-	      case LABEL_REF:
 	      case SYMBOL_REF:
-		switch (GET_CODE(y))
-		  {
-		    case CONST_INT:
-	 	      fprintf (file,"%d+%s",INTVAL(y),XSTR(x,0));
-	 	      break;
-		    case REG:
-		      fprintf (file,"%s,R%d ;P_O_A sym + reg",
-				 XSTR(x,0),REGNO(y));
-		      break;
-		    default:
-		      fprintf(file, "P_O_A sym/lab+UFO[sym=%s,code(y)=%d]",
-				 XSTR(x,0),GET_CODE(y));
-		  }
-	 	break;
-	      case CONST:
-	        output_address(XEXP(x,0));
-	        if (GET_CODE(y) == REG)
-		  fprintf(file, ",R%d ;P_O_A const + reg",REGNO(x));
-	        else
-		  fprintf(file,"P_O_A const+UFO code(y)=%d]",GET_CODE(y));
-	        break;
-	      case MEM:
-		output_address(y);
-		fprintf(file, ",[mem:");
-		output_address(XEXP(x,0));
-		fprintf(file, "] ;P_O_A plus");
+		fprintf (file, "%s,r%d  ; P_O_A reg + sym",
+			 XSTR (y, 0), REGNO (x));
 		break;
 	      default:
-		fprintf(file, "P_O_A plus op1_UFO[code1=%d,code2=%d]",
-			GET_CODE(x),GET_CODE(y));
-	    }
-	}
-	break;
-      case CONST_INT:
-	if (INTVAL(addr) < 0x10000 && INTVAL(addr) >= -0x10000)
-	  fprintf (file, "%d ; p_o_a const addr?!", INTVAL(addr));
-	else
-	  {
-	    fprintf(file,"[p_o_a=ILLEGAL_CONST]");
-	    output_addr_const (file, addr);
+		fprintf (file, "[P_O_A reg%d+UFO code=%d]",
+			 REGNO (x), GET_CODE (y));
+	      }
+	    break;
+	  case LABEL_REF:
+	  case SYMBOL_REF:
+	    switch (GET_CODE (y))
+	      {
+	      case CONST_INT:
+		fprintf (file, "%d+%s", INTVAL (y), XSTR (x, 0));
+		break;
+	      case REG:
+		fprintf (file, "%s,r%d ;P_O_A sym + reg",
+			 XSTR (x, 0), REGNO (y));
+		break;
+	      default:
+		fprintf (file, "P_O_A sym/lab+UFO[sym=%s,code(y)=%d]",
+			 XSTR (x, 0), GET_CODE (y));
+	      }
+	    break;
+	  case CONST:
+	    output_address (XEXP (x, 0));
+	    if (GET_CODE (y) == REG)
+	      fprintf (file, ",r%d ;P_O_A const + reg", REGNO (x));
+	    else
+	      fprintf (file, "P_O_A const+UFO code(y)=%d]", GET_CODE (y));
+	    break;
+	  case MEM:
+	    output_address (y);
+	    fprintf (file, ",[mem:");
+	    output_address (XEXP (x, 0));
+	    fprintf (file, "] ;P_O_A plus");
+	    break;
+	  default:
+	    fprintf (file, "P_O_A plus op1_UFO[code1=%d,code2=%d]",
+		     GET_CODE (x), GET_CODE (y));
 	  }
-	break;
-      case LABEL_REF:
-      case SYMBOL_REF:
-	fprintf(file,"%s",XSTR(addr,0));
-	break;
-      case MEM:
-	fprintf(file,"[memUFO:");
-	output_address(XEXP(addr,0));
-	fprintf(file,"]");
-	break;
-      case CONST:
-	output_address(XEXP(addr,0));
-	fprintf(file," ;P_O_A const");
-	break;
-      default:
-	fprintf(file," p_o_a UFO, code=%d val=0x%x",
-			(int) GET_CODE(addr),INTVAL(addr));
-	break;
+      }
+      break;
+    case CONST_INT:
+      if (INTVAL (addr) < 0x10000 && INTVAL (addr) >= -0x10000)
+	fprintf (file, "%d ; p_o_a const addr?!", INTVAL (addr));
+      else
+	{
+	  fprintf (file, "[p_o_a=ILLEGAL_CONST]");
+	  output_addr_const (file, addr);
+	}
+      break;
+    case LABEL_REF:
+    case SYMBOL_REF:
+      fprintf (file, "%s", XSTR (addr, 0));
+      break;
+    case MEM:
+      fprintf (file, "[memUFO:");
+      output_address (XEXP (addr, 0));
+      fprintf (file, "]");
+      break;
+    case CONST:
+      output_address (XEXP (addr, 0));
+      fprintf (file, " ;P_O_A const");
+      break;
+    default:
+      fprintf (file, " p_o_a UFO, code=%d val=0x%x",
+	       (int) GET_CODE (addr), INTVAL (addr));
+      break;
     }
 }
 
+
+/*
+ASM_FILE_END(file)
+  FILE *file;
+{
+      if (datalbl_ndx >= 0) {
+         int i, cum_size=0;
+         fprintf(file,"\n\tstatic\ninit_srel\n");
+         for (i = 0; i <= datalbl_ndx; i++) {
+	   if (datalbl[i].name == NULL)	
+	   {
+	     fprintf (stderr, "asm_file_end intern err (datalbl)\n");
+	     exit (0);
+	   }
+           fprintf(file,"%s\t block %d\n",
+                 datalbl[i].name,datalbl[i].size);
+           cum_size += datalbl[i].size;
+	 }
+         fprintf(file,"\n\tinit\n");
+         fprintf(file,"\tLIM  R0,init_srel ;dst\n");
+         fprintf(file,"\tLIM  R1,%d ;cnt\n",cum_size);
+         fprintf(file,"\tLIM  R2,K%s ;src\n",datalbl[0].name);
+         fprintf(file,"\tMOV  R0,R2\n");
+         fprintf(file,"\n\tnormal\n");
+         datalbl_ndx = -1;
+         for (i = 0; i < DATALBL_ARRSIZ; i++)
+            datalbl[i].size = 0;
+      }	
+      fprintf(file,"\n\tend\n");
+}
+ */
diff --git a/gcc/config/1750a/1750a.md b/gcc/config/1750a/1750a.md
index 95714d3..e2eb1dd 100644
--- a/gcc/config/1750a/1750a.md
+++ b/gcc/config/1750a/1750a.md
@@ -1,6 +1,7 @@
-;;- Machine description for GNU compiler, MIL-STD-1750A version.
-;;  Copyright (C) 1994 Free Software Foundation, Inc.
-;;  Contributed by O.M.Kellogg, Deutsche Aerospace (okellogg@salyko.cube.net).
+;;- Machine description for GNU compiler
+;;- MIL-STD-1750A version.
+;; Copyright (C) 1994 Free Software Foundation, Inc.
+;; Contributed by O.M.Kellogg, DASA (okellogg@salyko.cube.net).
 
 ;; This file is part of GNU CC.
 
@@ -53,7 +54,7 @@
   [(set (match_operand:QI 0 "push_operand" "=<")
         (match_operand:QI 1 "general_operand" "r"))]
   ""
-  "PSHM   R%1,R%1")
+  "pshm r%1,r%1")
 
 (define_insn ""
   [(set (match_operand:HI 0 "push_operand" "=<")
@@ -75,7 +76,7 @@
         rtx new_operands[2];
         new_operands[0] = operands[1];
         new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1);
-        output_asm_insn(\"PSHM   R%0,R%1\",new_operands);
+        output_asm_insn(\"pshm r%0,r%1\",new_operands);
         return \"\;\";
    } ")
 
@@ -88,7 +89,7 @@
         rtx new_operands[2];
         new_operands[0] = operands[1];
         new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+2);
-        output_asm_insn(\"PSHM   R%0,R%1\",new_operands);
+        output_asm_insn(\"pshm r%0,r%1\",new_operands);
         return \"\;\";
    } ")
 
@@ -97,7 +98,7 @@
   [(set (match_operand:QI 0 "general_operand" "=r")
         (match_operand:QI 1 "push_operand" ">"))]
   ""
-  "POPM   R%1,R%1")
+  "popm r%1,r%1")
 
 (define_insn ""
   [(set (match_operand:HI 0 "general_operand" "=r")
@@ -108,7 +109,7 @@
         rtx new_operands[2];
         new_operands[0] = operands[0];
         new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1);
-        output_asm_insn(\"POPM   R%0,R%1\",new_operands);
+        output_asm_insn(\"popm r%0,r%1\",new_operands);
         return \"\;\";
    } ")
 
@@ -121,7 +122,7 @@
         rtx new_operands[2];
         new_operands[0] = operands[0];
         new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1);
-        output_asm_insn(\"POPM   R%0,R%1\",new_operands);
+        output_asm_insn(\"popm r%0,r%1\",new_operands);
         return \"\;\";
    } ")
 
@@ -134,7 +135,7 @@
         rtx new_operands[2];
         new_operands[0] = operands[0];
         new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+2);
-        output_asm_insn(\"POPM   R%0,R%1\",new_operands);
+        output_asm_insn(\"popm r%0,r%1\",new_operands);
         return \"\;\";
    } ")
 
@@ -145,26 +146,26 @@
   [(set (cc0)
         (match_operand:QI 0 "register_operand" "r"))]
   ""
-  "LR     R%0,R%0   ; from tstqi")
+  "lr r%0,r%0   ; from tstqi")
 
 (define_insn "tsthi"
   [(set (cc0)
         (match_operand:HI 0 "register_operand" "r"))]
   ""
-  "DLR    R%0,R%0   ; from tsthi")
+  "dlr r%0,r%0   ; from tsthi")
 
 (define_insn "tsthf"
   [(set (cc0)
         (match_operand:HF 0 "register_operand" "r"))]
   ""
-  "DLR    R%0,R%0   ; from tsthf")
+  "dlr r%0,r%0   ; from tsthf")
 
 ;; This one is happy with "roughly zero" :-)  (should be improved)
 (define_insn "tsttqf"
   [(set (cc0)
         (match_operand:TQF 0 "register_operand" "r"))]
   ""
-  "DLR    R%0,R%0   ; from tsttqf")
+  "dlr r%0,r%0   ; from tsttqf")
 
 
 ;; block move.
@@ -192,11 +193,11 @@
                  (match_operand:QI 1 "general_operand"  "I,J,i,r,m")))]
   ""
   "@
-     CISP   R%0,%1
-     CISN   R%0,%J1
-     CIM    R%0,%1
-     CR     R%0,R%1
-     C      R%0,%1 ")
+     cisp r%0,%1
+     cisn r%0,%J1
+     cim  r%0,%1
+     cr   r%0,r%1
+     c    r%0,%1 ")
 
 (define_insn "cmphi"
   [(set (cc0)
@@ -204,8 +205,8 @@
                  (match_operand:HI 1 "general_operand" "r,m")))]
   ""
   "@
-    DCR    R%0,R%1
-    DC     R%0,%1 ")
+    dcr r%0,r%1
+    dc  r%0,%1 ")
 
 (define_insn "cmphf"
  [(set (cc0)
@@ -213,8 +214,8 @@
                 (match_operand:HF 1 "general_operand" "r,m")))]
  ""
  "@
-   FCR    R%0,R%1
-   FC     R%0,%1 ")
+   fcr r%0,r%1
+   fc  r%0,%1 ")
 
 (define_insn "cmptqf"
   [(set (cc0)
@@ -222,8 +223,8 @@
                  (match_operand:TQF 1 "general_operand" "r,m")))]
   ""
   "@
-    EFCR   R%0,R%1
-    EFC    R%0,%1 ")
+    efcr r%0,r%1
+    efc  r%0,%1 ")
 
 
 ;; truncation instructions
@@ -237,7 +238,7 @@
   "*
      {
         REGNO(operands[1]) += 1;
-        return \"LR     R%0,R%1  ;trunchiqi2\";
+        return \"lr r%0,r%1  ;trunchiqi2\";
      } ")
 
 ;; zero extension instructions
@@ -248,16 +249,16 @@
   ""
   "*
       {
-        output_asm_insn(\"XORR   R%0,R%0   ;zero_extendqihi2\",operands);
+        output_asm_insn(\"xorr r%0,r%0   ;zero_extendqihi2\",operands);
         REGNO(operands[0]) += 1;
         switch (which_alternative)
           {
             case 0:
-              return \"LR     R%0,R%1\";
+              return \"lr  r%0,r%1\";
             case 1:
-              return \"L      R%0,%1\";
+              return \"l   r%0,%1\";
             case 2:
-              return \"LIM    R%0,%1\";
+              return \"lim r%0,%1\";
           }
       } ")
 
@@ -268,9 +269,9 @@
         (sign_extend:HI (match_operand:QI 1 "general_operand" "r,m,i")) )]
   ""
   "@
-    LR     R%0,R%1 ;extendqihi2\;DSRA   R%0,16
-    L      R%0,%1  ;extendqihi2\;DSRA   R%0,16
-    LIM    R%0,%1  ;extendqihi2\;DSRA   R%0,16 ")
+    lr  r%0,r%1 ;extendqihi2\;dsra r%0,16
+    l   r%0,%1  ;extendqihi2\;dsra r%0,16
+    lim r%0,%1  ;extendqihi2\;dsra r%0,16 ")
 
 
 ;; Conversions between float and double.
@@ -284,12 +285,12 @@
   "*
       {
         REGNO(operands[0]) += 2;
-        output_asm_insn(\"XORR   R%0,R%0   ;extendhftqf2\",operands);
+        output_asm_insn(\"xorr r%0,r%0   ;extendhftqf2\",operands);
         REGNO(operands[0]) -= 2;
         if (which_alternative == 0)
-          return \"DLR    R%0,R%1\";
+          return \"dlr r%0,r%1\";
         else
-          return \"DL     R%0,%1\";
+          return \"dl  r%0,%1\";
       } ")
 
 ; 1750 TQF-to-HF truncate is a no-op: just leave away the least signif. 16 bits
@@ -299,8 +300,8 @@
           (match_operand:TQF 1 "general_operand" "r,m")))]
   ""
   "@
-     DLR    R%0,R%1  ;trunctqfhf2
-     DL     R%0,%1   ;trunctqfhf2 ")
+     dlr r%0,r%1  ;trunctqfhf2
+     dl  r%0,%1   ;trunctqfhf2 ")
 
 
 ;; Conversion between fixed point and floating point.
@@ -309,13 +310,13 @@
   [(set           (match_operand:HF 0 "register_operand" "=r")
         (float:HF (match_operand:QI 1 "register_operand" "r")))]
   ""
-  "FLT    R%0,R%1")
+  "flt r%0,r%1")
 
 (define_insn "floathitqf2"
   [(set           (match_operand:TQF 0 "register_operand" "=r")
         (float:TQF (match_operand:HI 1 "register_operand" "r")))]
   ""
-  "EFLT   R%0,R%1")
+  "eflt r%0,r%1")
 
 
 ;; Convert floats to ints
@@ -324,13 +325,13 @@
   [(set                 (match_operand:QI 0 "register_operand" "=r")
         (fix:QI (fix:HF (match_operand:HF 1 "register_operand" "r"))))]
   ""
-  "FIX    R%0,R%1")
+  "fix r%0,r%1")
 
 (define_insn "fix_trunctqfhi2"
   [(set                 (match_operand:HI 0 "register_operand" "=r")
         (fix:HI (fix:TQF (match_operand:TQF 1 "register_operand" "r"))))]
   ""
-  "EFIX   R%0,R%1")
+  "efix r%0,r%1")
 
 
 ;; Move instructions
@@ -346,15 +347,15 @@
         (match_operand:QI 1 "general_operand"  "O,I,J,M,i,r,m,r,K"))]
   ""
   "@
-     XORR   R%0,R%0
-     LISP   R%0,%1
-     LISN   R%0,%J1
-     LIM    R%0,%1  ; 'M' constraint
-     LIM    R%0,%1  ; 'i' constraint
-     LR     R%0,R%1
-     L      R%0,%1
-     ST     R%1,%0
-     STC    %1,%0   ")
+     xorr r%0,r%0
+     lisp r%0,%1
+     lisn r%0,%J1
+     lim  r%0,%1  ; 'M' constraint
+     lim  r%0,%1  ; 'i' constraint
+     lr   r%0,r%1
+     l    r%0,%1
+     st   r%1,%0
+     stc  %1,%0   ")
 
 ;; 32-bit moves
 
@@ -371,25 +372,25 @@
           {
             if (val <= 65535)
               {
-                output_asm_insn(\"XORR   R%0,R%0 ;movhi cst->reg\",operands);
+                output_asm_insn(\"xorr   r%0,r%0 ;movhi cst->reg\",operands);
                 operands[0] = gen_rtx(REG,QImode,REGNO(operands[0]) + 1);
                 if (val == 0)
-                  return \"XORR   R%0,R%0\";
+                  return \"xorr r%0,r%0\";
                 else if (val <= 16)
-                  return \"LISP   R%0,%1\";
+                  return \"lisp r%0,%1\";
                 else
-                  return \"LIM    R%0,%1\";
+                  return \"lim  r%0,%1\";
               }
           }
         else if (val >= -16)
-          return \"LISN   R%0,%J1\;DSRA   R%0,16 ;movhi cst\";
+          return \"lisn r%0,%J1\;dsra r%0,16 ;movhi cst\";
         INTVAL(operands[1]) >>= 16;
-        output_asm_insn(\"LIM    R%0,%1 ;movhi cst->reg\",operands);
+        output_asm_insn(\"lim r%0,%1 ;movhi cst->reg\",operands);
         REGNO(operands[0]) += 1;
         INTVAL(operands[1]) = val & 0xFFFF;
-        return \"LIM    R%0,%1\";
+        return \"lim r%0,%1\";
       }
-    return \"LIM    R%0,%1\;DSRA   R%0,16 ;movhi cst\";
+    return \"lim r%0,%1\;dsra r%0,16 ;movhi cst\";
   ")
 
 (define_insn "movhi"
@@ -397,36 +398,53 @@
         (match_operand:HI 1 "general_operand"  "r,m,r"))]
   ""
   "@
-    DLR    R%0,R%1
-    DL     R%0,%1
-    DST    R%1,%0 ")
+    dlr r%0,r%1
+    dl  r%0,%1
+    dst r%1,%0 ")
 
 
 ;; Single-Float moves are *same* as HImode moves:
 
+;(define_insn "movhf"
+;  [(set (match_operand:HF 0 "general_operand" "=r,r,r,m")
+;        (match_operand:HF 1 "general_operand"  "F,r,m,r"))]
+;  ""
+;  "@
+;    %D1\;dl r%0,%F1
+;    dlr r%0,r%1
+;    dl  r%0,%1
+;    dst r%1,%0 ")
+
 (define_insn "movhf"
-  [(set (match_operand:HF 0 "general_operand" "=r,r,r,r,m")
-        (match_operand:HF 1 "general_operand"  "G,F,r,m,r"))]
+  [(set (match_operand:HF 0 "general_operand" "=r,r,m")
+        (match_operand:HF 1 "general_operand"  "r,m,r"))]
   ""
   "@
-    DXRR.M %0,%0 ; movhf const(0.0)
-    %E1\;DL     R%0,%F1
-    DLR    R%0,R%1
-    DL     R%0,%1
-    DST    R%1,%0 ")
+    dlr r%0,r%1
+    dl  r%0,%1
+    dst r%1,%0 ")
 
 
 ;; Longfloat moves
 
+;(define_insn "movtqf"
+;  [(set (match_operand:TQF 0 "general_operand" "=r,r,r,m")
+;        (match_operand:TQF 1 "general_operand"  "F,r,m,r"))]
+;  ""
+;  "@
+;    %E1\;efl r%0,%G1
+;    eflr.m %0,%1
+;    efl  r%0,%1
+;    efst r%1,%0 ")
+
 (define_insn "movtqf"
-  [(set (match_operand:TQF 0 "general_operand" "=r,r,r,m")
-        (match_operand:TQF 1 "general_operand"  "F,r,m,r"))]
+  [(set (match_operand:TQF 0 "general_operand" "=r,r,m")
+        (match_operand:TQF 1 "general_operand"  "r,m,r"))]
   ""
   "@
-    %D1\;EFL    R%0,%F1
-    EFLR.M %0,%1
-    EFL    R%0,%1
-    EFST   R%1,%0 ")
+    eflr.m %0,%1
+    efl  r%0,%1
+    efst r%1,%0 ")
 
 
 ;; add instructions 
@@ -440,7 +458,7 @@
 ;        (plus:QI (match_operand:QI 1 "register_operand" "b")
 ;                 (match_operand:QI 2 "immediate_operand"  "i")))]
 ;   "REGNO(operands[0]) != REGNO(operands[1])"
-;   "LIM    R%0,%2,R%1 ;md special addqi")
+;   "lim r%0,%2,r%1 ;md special addqi")
 
 (define_insn "addqi3"
   [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,m,m")
@@ -451,22 +469,22 @@
     switch (which_alternative)
       {
         case 0:
-          return \"AISP   R%0,%2\";
+          return \"aisp r%0,%2\";
         case 1:
-          return \"SISP   R%0,%J2\";
+          return \"sisp r%0,%J2\";
         case 2:
           if (INTVAL(operands[2]) < 0)
-            return \"SIM    R%0,%J2\";
+            return \"sim r%0,%J2\";
           else
-            return \"AIM    R%0,%2\";
+            return \"aim r%0,%2\";
         case 3:
-          return \"AR     R%0,R%2\";
+          return \"ar r%0,r%2\";
         case 4:
-          return \"A      R%0,%2\";
+          return \"a r%0,%2\";
         case 5:
-          return \"INCM   %2,%0\";
+          return \"incm %2,%0\";
         case 6:
-          return \"DECM   %J2,%0\";
+          return \"decm %J2,%0\";
       } ")
 
 ;; double integer
@@ -476,8 +494,8 @@
                  (match_operand:HI 2 "general_operand" "r,m")))]
   ""
   "@
-    DAR    R%0,R%2
-    DA     R%0,%2 ")
+    dar r%0,r%2
+    da  r%0,%2 ")
 
 (define_insn "addhf3"
   [(set (match_operand:HF 0 "register_operand" "=r,r")
@@ -485,8 +503,8 @@
                  (match_operand:HF 2 "general_operand" "m,r")))]
   ""
   "@
-    FA     R%0,%2
-    FAR    R%0,R%2 ")
+    fa  r%0,%2
+    far r%0,r%2 ")
 
 (define_insn "addtqf3"
   [(set (match_operand:TQF 0 "register_operand" "=r,r")
@@ -494,8 +512,8 @@
                  (match_operand:TQF 2 "general_operand" "m,r")))]
   ""
   "@
-    EFA    R%0,%2
-    EFAR   R%0,R%2 ")
+    efa  r%0,%2
+    efar r%0,r%2 ")
 
 
 ;; subtract instructions
@@ -507,11 +525,11 @@
                   (match_operand:QI 2 "general_operand"  "I,i,r,m,I")))]
   ""
   "@
-    SISP   R%0,%2
-    SIM    R%0,%2
-    SR     R%0,R%2
-    S      R%0,%2
-    DECM   %2,%0 ")
+    sisp r%0,%2
+    sim  r%0,%2
+    sr   r%0,r%2
+    s    r%0,%2
+    decm %2,%0 ")
 
 ;; double integer
 (define_insn "subhi3"
@@ -520,8 +538,8 @@
                   (match_operand:HI 2 "general_operand" "r,m")))]
   ""
   "@
-    DSR    R%0,R%2
-    DS     R%0,%2 ")
+    dsr r%0,r%2
+    ds  r%0,%2 ")
 
 (define_insn "subhf3"
   [(set (match_operand:HF 0 "register_operand" "=r,r")
@@ -529,8 +547,8 @@
                   (match_operand:HF 2 "general_operand" "r,m")))]
   ""
   "@
-    FSR    R%0,R%2
-    FS     R%0,%2 ")
+    fsr r%0,r%2
+    fs  r%0,%2 ")
 
 (define_insn "subtqf3"
   [(set (match_operand:TQF 0 "register_operand" "=r,r")
@@ -538,8 +556,8 @@
                   (match_operand:TQF 2 "general_operand" "r,m")))]
   ""
   "@
-    EFSR   R%0,R%2
-    EFS    R%0,%2 ")
+    efsr r%0,r%2
+    efs  r%0,%2 ")
 
 
 ;; multiply instructions
@@ -550,11 +568,11 @@
                  (match_operand:QI 2 "general_operand"  "I,J,M,r,m")))]
   ""
   "@
-     MISP   R%0,%2
-     MISN   R%0,%J2
-     MSIM   R%0,%2
-     MSR    R%0,R%2
-     MS     R%0,%2  ")
+     misp r%0,%2
+     misn r%0,%J2
+     msim r%0,%2
+     msr  r%0,r%2
+     ms   r%0,%2  ")
 
 
 ; 32-bit product
@@ -564,9 +582,9 @@
                  (match_operand:QI 2 "general_operand" "M,r,m")))]
   ""
   "@
-    MIM    R%0,%1
-    MR     R%0,R%2
-    M      R%0,%2 ")
+    mim r%0,%1
+    mr  r%0,r%2
+    m   r%0,%2 ")
 
 (define_insn "mulhi3"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
@@ -574,8 +592,8 @@
                  (match_operand:HI 2 "general_operand" "r,m")))]
   ""
   "@
-    DMR    R%0,R%2
-    DM     R%0,%2 ")
+    dmr r%0,r%2
+    dm  r%0,%2 ")
 
 ; not available on 1750: "umulhi3","umulhisi3","umulsi3" (unsigned multiply's)
 
@@ -585,8 +603,8 @@
                  (match_operand:HF 2 "general_operand" "r,m")))]
   ""
   "@
-    FMR    R%0,R%2
-    FM     R%0,%2 ")
+    fmr r%0,r%2
+    fm  r%0,%2 ")
 
 (define_insn "multqf3"
   [(set (match_operand:TQF 0 "register_operand" "=r,r")
@@ -594,8 +612,8 @@
                  (match_operand:TQF 2 "general_operand" "r,m")))]
   ""
   "@
-    EFMR   R%0,R%2
-    EFM    R%0,%2 ")
+    efmr r%0,r%2
+    efm  r%0,%2 ")
 
 
 ;; divide instructions
@@ -621,20 +639,20 @@
      switch(which_alternative)
        {
        case 0:
-         istr = \"DISP\";
+         istr = \"disp\";
          break;
        case 1:
          INTVAL(operands[2]) = - INTVAL(operands[2]); /* to be corrected */
-         istr = \"DISN\";
+         istr = \"disn\";
          break;
        case 2:
-         istr = \"DVIM\";
+         istr = \"dvim\";
          break;
        case 3:
-         istr = \"DVR \";
+         istr = \"dvr \";
          break;
        case 4:
-         istr = \"DV  \";
+         istr = \"dv  \";
          break;
       }
       return (char *)mod_regno_adjust(istr,operands);
@@ -648,8 +666,8 @@
                 (match_operand:HI 2 "general_operand" "r,m")))]
   ""
   "@
-    DDR    R%0,R%2
-    DD     R%0,%2 ")
+    ddr r%0,r%2
+    dd  r%0,%2 ")
 
 (define_insn "divhf3"
   [(set (match_operand:HF 0 "register_operand" "=r,r")
@@ -657,8 +675,8 @@
                 (match_operand:HF 2 "general_operand" "r,m")))]
   ""
   "@
-    FDR    R%0,R%2
-    FD     R%0,%2 ")
+    fdr r%0,r%2
+    fd  r%0,%2 ")
 
 (define_insn "divtqf3"
   [(set (match_operand:TQF 0 "register_operand" "=r,r")
@@ -666,8 +684,8 @@
                 (match_operand:TQF 2 "general_operand" "r,m")))]
   ""
   "@
-    EFDR   R%0,R%2
-    EFD    R%0,%2 ")
+    efdr r%0,r%2
+    efd  r%0,%2 ")
 
 
 ;; Other arithmetic instructions:
@@ -678,19 +696,19 @@
   [(set (match_operand:QI 0 "register_operand" "=r")
         (abs:QI (match_operand:QI 1 "register_operand" "r")))]
   ""
-  "ABS    R%0,R%1")
+  "abs r%0,r%1")
 
 (define_insn "abshi2"
   [(set (match_operand:HI 0 "register_operand" "=r")
         (abs:HI (match_operand:HI 1 "register_operand" "r")))]
   ""
-  "DABS   R%0,R%1")
+  "dabs r%0,r%1")
 
 (define_insn "abshf2"
   [(set (match_operand:HF 0 "register_operand" "=r")
         (abs:HF (match_operand:HF 1 "register_operand" "r")))]
   ""
-  "FABS   R%0,R%1")
+  "fabs r%0,r%1")
 
 
 ;; Negation
@@ -699,31 +717,31 @@
   [(set (match_operand:QI 0 "register_operand" "=r")
         (neg:QI (match_operand:QI 1 "register_operand" "r")))]
   ""
-  "NEG    R%0,R%1")
+  "neg r%0,r%1")
 
 (define_insn "neghi2"
   [(set (match_operand:HI 0 "register_operand" "=r")
         (neg:HI (match_operand:HI 1 "register_operand" "r")))]
   ""
-  "DNEG   R%0,R%1")
+  "dneg r%0,r%1")
 
 (define_insn "neghf2"
   [(set (match_operand:HF 0 "register_operand" "=r")
         (neg:HF (match_operand:HF 1 "register_operand" "r")))]
   ""
-  "FNEG   R%0,R%1")
+  "fneg r%0,r%1")
 
 ; The 1750A does not have an extended float negate instruction, so simulate.
-;(define_expand "negtqf2"
-;  [(set (match_operand:TQF 0 "register_operand" "=&r")
-;        (neg:TQF (match_operand:TQF 1 "register_operand" "r")))]
-;  ""
-;  "
-;   emit_insn(gen_rtx(SET,VOIDmode,operands[0],CONST0_RTX(TQFmode)));
-;   emit_insn(gen_rtx(SET,VOIDmode,operands[0],
-;             gen_rtx(MINUS,TQFmode,operands[0],operands[1])));
-;   DONE;
-;  ")
+(define_expand "negtqf2"
+  [(set (match_operand:TQF 0 "register_operand" "=&r")
+        (neg:TQF (match_operand:TQF 1 "register_operand" "r")))]
+  ""
+  "
+   emit_insn(gen_rtx(SET,VOIDmode,operands[0],CONST0_RTX(TQFmode)));
+   emit_insn(gen_rtx(SET,VOIDmode,operands[0],
+             gen_rtx(MINUS,TQFmode,operands[0],operands[1])));
+   DONE;
+  ")
 
 
 ;; bit-logical instructions
@@ -736,9 +754,9 @@
                 (match_operand:QI 2 "general_operand" "M,r,m")))]
   ""
   "@
-    ANDM   R%0,%2
-    ANDR   R%0,R%2
-    AND    R%0,%2 ")
+    andm r%0,%2
+    andr r%0,r%2
+    and  r%0,%2 ")
 
 ; This sets incorrect condition codes. See notice_update_cc()
 (define_insn "andhi3"
@@ -746,7 +764,7 @@
         (and:HI (match_operand:HI 1 "register_operand" "%0")
                 (match_operand:HI 2 "register_operand" "r")))]
   ""
-  "DANR.M %0,%2")
+  "danr.m %0,%2")
 
 ;; OR
 
@@ -756,9 +774,9 @@
                 (match_operand:QI 2 "general_operand" "M,r,m")))]
   ""
   "@
-    ORIM   R%0,%2
-    ORR    R%0,R%2
-    OR     R%0,%2 ")
+    orim r%0,%2
+    orr  r%0,r%2
+    or   r%0,%2 ")
 
 ; This sets incorrect condition codes. See notice_update_cc()
 (define_insn "iorhi3"
@@ -766,7 +784,7 @@
         (ior:HI (match_operand:HI 1 "register_operand" "%0")
                 (match_operand:HI 2 "register_operand" "r")))]
   ""
-  "DORR.M %0,%2")
+  "dorr.m %0,%2")
 
 ;; XOR
 
@@ -776,9 +794,9 @@
                 (match_operand:QI 2 "general_operand"  "M,r,m")))]
   ""
   "@
-    XORM   R%0,%2
-    XORR   R%0,R%2
-    XOR    R%0,%2 ")
+    xorm r%0,%2
+    xorr r%0,r%2
+    xor  r%0,%2 ")
 
 ; This sets incorrect condition codes. See notice_update_cc()
 (define_insn "xorhi3"
@@ -786,7 +804,7 @@
         (xor:HI (match_operand:HI 1 "register_operand" "%0")
                 (match_operand:HI 2 "register_operand" "r")))]
   ""
-  "DXRR.M %0,%2")
+  "dxrr.m %0,%2")
 
 ;; NAND
 
@@ -796,9 +814,9 @@
 		(not:QI (match_operand:QI 2 "general_operand" "M,r,m"))))]
   ""
   "@
-    NIM    R%0,%2
-    NR     R%0,R%2
-    N      R%0,%2 ")
+    nim r%0,%2
+    nr  r%0,r%2
+    n   r%0,%2 ")
 
 ; This sets incorrect condition codes. See notice_update_cc()
 (define_insn ""
@@ -806,7 +824,7 @@
 	(ior:HI (not:HI (match_operand:HI 1 "register_operand" "%0"))
 		(not:HI (match_operand:HI 2 "register_operand" "r"))))]
   ""
-  "DNR.M  %0,%2")
+  "dnr.m %0,%2")
 
 ;; NOT
 
@@ -814,14 +832,14 @@
   [(set (match_operand:QI 0 "register_operand" "=r")
         (not:QI (match_operand:QI 1 "register_operand" "0")))]
   ""
-  "NR     R%0,R%0")
+  "nr r%0,r%0")
 
 ; This sets incorrect condition codes. See notice_update_cc()
 (define_insn "one_cmplhi2"
   [(set (match_operand:HI 0 "register_operand" "=r")
         (not:HI (match_operand:HI 1 "register_operand" "0")))]
   ""
-  "DNR.M  %0,%0")
+  "dnr.m %0,%0")
 
 
 ;; Shift instructions
@@ -833,9 +851,9 @@
                    (match_operand:QI 2 "general_operand" "O,I,r")))]
   ""
   "@
-    ; optimized away an SLL R%0,0
-    SLL    R%0,%2
-    SLR    R%0,R%2 ")
+    ; optimized away an SLL r%0,0
+    sll r%0,%2
+    slr r%0,r%2 ")
 
 (define_insn "ashlhi3"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
@@ -843,8 +861,8 @@
                    (match_operand:QI 2 "general_operand" "L,r")))]
   ""                        ; the 'L' constraint is a slight imprecise...
   "@
-     DSLL   R%0,%2
-     DSLR   R%0,R%2 ")
+     dsll r%0,%2
+     dslr r%0,r%2 ")
 
 (define_insn "lshrqi3"
   [(set (match_operand:QI 0 "register_operand" "=r,r")
@@ -852,8 +870,8 @@
                      (match_operand:QI 2 "general_operand" "I,r")))]
   ""
   "@
-    SRL    R%0,%2
-    NEG    R%2,R%2\;SLR    R%0,R%2 ")
+    srl r%0,%2
+    neg r%2,r%2\;slr    r%0,r%2 ")
 
 (define_insn "lshrhi3"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
@@ -861,8 +879,8 @@
                      (match_operand:QI 2 "general_operand" "L,r")))]
   ""                        ; the 'L' constraint is a slight imprecise...
   "@
-    DSRL   R%0,%2
-    NEG    R%2,R%2\;DSLR   R%0,R%2 ")
+    dsrl r%0,%2
+    neg  r%2,r%2\;dslr   r%0,r%2 ")
 
 (define_insn "ashrqi3"
   [(set (match_operand:QI 0 "register_operand" "=r,r")
@@ -870,8 +888,8 @@
                      (match_operand:QI 2 "general_operand" "I,r")))]
   ""
   "@
-     SRA    R%0,%2
-     NEG    R%2,R%2\;SAR    R%0,R%2 ")
+     sra r%0,%2
+     neg r%2,r%2\;sar    r%0,r%2 ")
 
 (define_insn "ashrhi3"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
@@ -879,8 +897,8 @@
                      (match_operand:QI 2 "general_operand" "I,r")))]
   ""
   "@
-     DSRA   R%0,%2
-     NEG    R%2,R%2\;DSAR   R%0,R%2 ")
+     dsra r%0,%2
+     neg  r%2,r%2\;dsar   r%0,r%2 ")
 
 
 ;; rotate instructions
@@ -891,8 +909,8 @@
                    (match_operand:QI 2 "general_operand" "I,r")))]
   ""
   "@
-    SLC    R%0,%2
-    SCR    R%0,R%2 ")
+    slc r%0,%2
+    scr r%0,r%2 ")
 
 (define_insn "rotlhi3"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
@@ -900,8 +918,8 @@
                    (match_operand:QI 2 "general_operand" "I,r")))]
   ""
   "@
-    DSLC   R%0,%2
-    DSCR   R%0,R%2 ")
+    dslc r%0,%2
+    dscr r%0,r%2 ")
 
 (define_insn "rotrqi3"
   [(set (match_operand:QI 0 "register_operand" "=r,r")
@@ -909,8 +927,8 @@
                      (match_operand:QI 2 "general_operand" "I,r")))]
   ""
   "@
-    SLC    R%0,%2
-    NEG    R%2,R%2\;SCR    R%0,R%2 ")
+    slc r%0,%2
+    neg r%2,r%2\;scr    r%0,r%2 ")
 
 (define_insn "rotrhi3"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
@@ -918,8 +936,8 @@
                      (match_operand:QI 2 "general_operand" "I,r")))]
   ""
   "@
-    DSLC   R%0,%2
-    NEG    R%2,R%2\;DSCR   R%0,R%2 ")
+    dslc r%0,%2
+    neg  r%2,r%2\;dscr   r%0,r%2 ")
 
 
 
@@ -964,7 +982,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "* return (char *)branch_or_jump(\"EZ\",CODE_LABEL_NUMBER(operands[0]));
+  "* return (char *)branch_or_jump(\"ez\",CODE_LABEL_NUMBER(operands[0]));
   ")
 
 (define_insn "bne"
@@ -974,7 +992,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "* return (char *)branch_or_jump(\"NZ\",CODE_LABEL_NUMBER(operands[0]));
+  "* return (char *)branch_or_jump(\"nz\",CODE_LABEL_NUMBER(operands[0]));
   ")
 
 (define_insn "bgt"
@@ -984,7 +1002,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "* return (char *)branch_or_jump(\"GT\",CODE_LABEL_NUMBER(operands[0]));
+  "* return (char *)branch_or_jump(\"gt\",CODE_LABEL_NUMBER(operands[0]));
   ")
 
 (define_insn "blt"
@@ -994,7 +1012,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "* return (char *)branch_or_jump(\"LT\",CODE_LABEL_NUMBER(operands[0]));
+  "* return (char *)branch_or_jump(\"lt\",CODE_LABEL_NUMBER(operands[0]));
   ")
 
 (define_insn "bge"
@@ -1004,7 +1022,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "* return (char *)branch_or_jump(\"GE\",CODE_LABEL_NUMBER(operands[0]));
+  "* return (char *)branch_or_jump(\"ge\",CODE_LABEL_NUMBER(operands[0]));
   ")
 
 (define_insn "ble"
@@ -1014,7 +1032,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "* return (char *)branch_or_jump(\"LE\",CODE_LABEL_NUMBER(operands[0]));
+  "* return (char *)branch_or_jump(\"le\",CODE_LABEL_NUMBER(operands[0]));
   ")
 
 
@@ -1027,7 +1045,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "JC     GT,%l0 ; Warning: this should be an *unsigned* test!")
+  "jc gt,%l0 ; Warning: this should be an *unsigned* test!")
 
 (define_insn "bltu"
   [(set (pc)
@@ -1036,7 +1054,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "JC     LT,%l0 ; Warning: this should be an *unsigned* test!")
+  "jc lt,%l0 ; Warning: this should be an *unsigned* test!")
 
 (define_insn "bgeu"
   [(set (pc)
@@ -1045,7 +1063,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "JC     GE,%l0 ; Warning: this should be an *unsigned* test!")
+  "jc ge,%l0 ; Warning: this should be an *unsigned* test!")
 
 (define_insn "bleu"
   [(set (pc)
@@ -1054,7 +1072,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "JC     LE,%l0 ; Warning: this should be an *unsigned* test!")
+  "jc le,%l0 ; Warning: this should be an *unsigned* test!")
 
 
 ;; Negated conditional jump instructions.
@@ -1066,7 +1084,7 @@
                       (pc)
                       (label_ref (match_operand 0 "" ""))))]
   ""
-  "* return (char *)branch_or_jump(\"NZ\",CODE_LABEL_NUMBER(operands[0]));
+  "* return (char *)branch_or_jump(\"nz\",CODE_LABEL_NUMBER(operands[0]));
   ")
 
 (define_insn ""
@@ -1076,7 +1094,7 @@
                       (pc)
                       (label_ref (match_operand 0 "" ""))))]
   ""
-  "* return (char *)branch_or_jump(\"EZ\",CODE_LABEL_NUMBER(operands[0]));
+  "* return (char *)branch_or_jump(\"ez\",CODE_LABEL_NUMBER(operands[0]));
   ")
 
 (define_insn ""
@@ -1086,7 +1104,7 @@
                       (pc)
                       (label_ref (match_operand 0 "" ""))))]
   ""
-  "* return (char *)branch_or_jump(\"LE\",CODE_LABEL_NUMBER(operands[0]));
+  "* return (char *)branch_or_jump(\"le\",CODE_LABEL_NUMBER(operands[0]));
   ")
 
 (define_insn ""
@@ -1096,7 +1114,7 @@
                       (pc)
                       (label_ref (match_operand 0 "" ""))))]
   ""
-  "* return (char *)branch_or_jump(\"GE\",CODE_LABEL_NUMBER(operands[0]));
+  "* return (char *)branch_or_jump(\"ge\",CODE_LABEL_NUMBER(operands[0]));
   ")
 
 (define_insn ""
@@ -1106,7 +1124,7 @@
                       (pc)
                       (label_ref (match_operand 0 "" ""))))]
   ""
-  "* return (char *)branch_or_jump(\"LT\",CODE_LABEL_NUMBER(operands[0]));
+  "* return (char *)branch_or_jump(\"lt\",CODE_LABEL_NUMBER(operands[0]));
   ")
 
 (define_insn ""
@@ -1116,7 +1134,7 @@
                       (pc)
                       (label_ref (match_operand 0 "" ""))))]
   ""
-  "* return (char *)branch_or_jump(\"GT\",CODE_LABEL_NUMBER(operands[0]));
+  "* return (char *)branch_or_jump(\"gt\",CODE_LABEL_NUMBER(operands[0]));
   ")
 
 
@@ -1129,7 +1147,7 @@
                       (pc)
                       (label_ref (match_operand 0 "" ""))))]
   ""
-  "JC     LE,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
+  "jc le,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
 
 (define_insn ""
   [(set (pc)
@@ -1138,7 +1156,7 @@
                       (pc)
                       (label_ref (match_operand 0 "" ""))))]
   ""
-  "JC     GE,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
+  "jc ge,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
 
 (define_insn ""
   [(set (pc)
@@ -1147,7 +1165,7 @@
                       (pc)
                       (label_ref (match_operand 0 "" ""))))]
   ""
-  "JC     LT,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
+  "jc lt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
 
 (define_insn ""
   [(set (pc)
@@ -1156,7 +1174,7 @@
                       (pc)
                       (label_ref (match_operand 0 "" ""))))]
   ""
-  "JC     GT,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
+  "jc gt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
 
 ;; Tablejump 
 ;; 1750 note: CASE_VECTOR_PC_RELATIVE is not defined
@@ -1165,7 +1183,7 @@
         (match_operand:QI 0 "register_operand" "b"))
    (use (label_ref (match_operand 1 "" "")))]
   ""
-  "JC     15,0,R%0   ; tablejump label_ref=%1")
+  "jc 15,0,r%0   ; tablejump label_ref=%1")
 
 
 ;; Unconditional jump
@@ -1173,7 +1191,7 @@
   [(set (pc)
         (label_ref (match_operand 0 "" "")))]
   ""
-  "JC     UC,%0")
+  "jc uc,%0")
 
 ;; Call subroutine, returning value in operand 0
 ;; (which must be a hard register).
@@ -1183,7 +1201,7 @@
               (match_operand:QI 2 "general_operand" "g")))]
   ;; Operand 2 not really used for 1750.
   ""
-  "SJS    R15,%1   ; return value in R0")
+  "sjs r15,%1   ; return value in R0")
 
 ;; Call subroutine with no return value.
 
@@ -1192,7 +1210,7 @@
   [(call (match_operand:QI 0 "memory_operand" "mp")
          (match_operand:QI 1 "general_operand" ""))]
   ""
-  "SJS    R15,%0   ; no return value")
+  "sjs r15,%0   ; no return value")
 
 ;;;;;;;;;;;; 1750: NOT READY YET.
 (define_insn "call"
@@ -1208,14 +1226,14 @@
 ;   "*
 ;    { 
 ;         rtx oprnd = gen_rtx(CONST_INT,VOIDmode,get_frame_size());
-;         output_asm_insn(\"RET.M  %0\",&oprnd);
+;         output_asm_insn(\"ret.m  %0\",&oprnd);
 ;         return \"\;\";
 ;    } ")
 
 (define_insn "indirect_jump"
   [(set (pc) (match_operand:QI 0 "address_operand" "p"))]
   ""
-  "JCI   15,%0")
+  "jci 15,%0")
 
 (define_insn "nop"
   [(const_int 0)]
@@ -1235,7 +1253,7 @@
          (pc)))
    ]
   "INTVAL(operands[2]) == -1"
-  "SOJ    R%0,%3")
+  "soj r%0,%3")
 
 ;;;End.