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authorJoern Rennecke <amylaar@gcc.gnu.org>1996-12-13 19:46:28 +0000
committerJoern Rennecke <amylaar@gcc.gnu.org>1996-12-13 19:46:28 +0000
commitaff48e325b97d4c110288999734958f7eaa4142b (patch)
treef9a259dc01bfda90889d6743bfc9fd5eb8e8b4f9 /gcc
parent5c8c0abd1ffe7eccbdfa464803e4360d37563c7e (diff)
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(dect): Rewrite pattern so that it can be combined.
From-SVN: r13307
Diffstat (limited to 'gcc')
-rw-r--r--gcc/config/sh/sh.md17
1 files changed, 3 insertions, 14 deletions
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 07bc69a..6c75623 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -222,10 +222,6 @@
""
"movt %0")
-;; ??? This combiner pattern does not work, because combine does not combine
-;; instructions that set a hard register when SMALL_REGISTER_CLASSES is
-;; defined. Perhaps use a pseudo-reg for the T bit?
-
(define_insn ""
[(set (reg:SI 18)
(eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
@@ -2108,17 +2104,10 @@
;; Misc insns
;; ------------------------------------------------------------------------
-;; ??? This combiner pattern does not work, because combine does not combine
-;; instructions that set a hard register when SMALL_REGISTER_CLASSES is
-;; defined. Perhaps use a pseudo-reg for the T bit?
-
(define_insn "dect"
- [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "=r")
- (plus:SI (match_dup 0)
- (const_int -1)))
- (set (reg:SI 18)
- (eq:SI (plus:SI (match_dup 0) (const_int -1))
- (const_int 0)))])]
+ [(set (reg:SI 18)
+ (eq:SI (match_operand:SI 0 "arith_reg_operand" "+r") (const_int 1)))
+ (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
"TARGET_SH2"
"dt %0")