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| author | Daniel Cederman <cederman@gaisler.com> | 2017-11-29 15:20:48 +0000 |
|---|---|---|
| committer | Daniel Hellstrom <danielh@gcc.gnu.org> | 2017-11-29 16:20:48 +0100 |
| commit | aed173734df52b9c48425840c0977c34c23a882a (patch) | |
| tree | a51fe30ab1b4d438efdacf076686e750da4ba9c8 /gcc | |
| parent | dcacda0cc1c9ecd23c15e8403e8025129502fed9 (diff) | |
| download | gcc-aed173734df52b9c48425840c0977c34c23a882a.zip gcc-aed173734df52b9c48425840c0977c34c23a882a.tar.gz gcc-aed173734df52b9c48425840c0977c34c23a882a.tar.bz2 | |
[SPARC] Errata workaround for GRLIB-TN-0011
This patch provides a workaround for the errata described in GRLIB-TN-0011.
If the workaround is enabled it will:
* Insert .align 16 before atomic instructions (swap, ldstub, casa).
It is applicable to GR712RC.
2017-11-29 Daniel Cederman <cederman@gaisler.com>
gcc/
* config/sparc/sync.md (swapsi): 16-byte align if sparc_fix_gr712rc.
(atomic_compare_and_swap_leon3_1): Likewise.
(ldstub): Likewise.
From-SVN: r255235
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/sparc/sync.md | 28 |
2 files changed, 29 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 390a0b7..02cb730 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2017-11-29 Daniel Cederman <cederman@gaisler.com> + * config/sparc/sync.md (swapsi): 16-byte align if sparc_fix_gr712rc. + (atomic_compare_and_swap_leon3_1): Likewise. + (ldstub): Likewise. + +2017-11-29 Daniel Cederman <cederman@gaisler.com> + * config/sparc/sparc.c (fpop_insn_p): New function. (sparc_do_work_around_errata): Insert NOP instructions to prevent sequences that could trigger the TN-0012 errata for diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md index 1593bde..ead7c77 100644 --- a/gcc/config/sparc/sync.md +++ b/gcc/config/sparc/sync.md @@ -222,12 +222,16 @@ UNSPECV_CAS))] "TARGET_LEON3" { + if (sparc_fix_gr712rc) + output_asm_insn (".align\t16", operands); if (TARGET_SV_MODE) return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space. */ else return "casa\t%1 0xa, %2, %0"; /* ASI for user data space. */ } - [(set_attr "type" "multi")]) + [(set_attr "type" "multi") + (set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true") + (const_int 4) (const_int 1)))]) (define_insn "*atomic_compare_and_swapdi_v8plus" [(set (match_operand:DI 0 "register_operand" "=h") @@ -275,8 +279,15 @@ (set (match_dup 1) (match_operand:SI 2 "register_operand" "0"))] "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699" - "swap\t%1, %0" - [(set_attr "type" "multi")]) +{ + if (sparc_fix_gr712rc) + return ".align\t16\n\tswap\t%1, %0"; + else + return "swap\t%1, %0"; +} + [(set_attr "type" "multi") + (set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true") + (const_int 4) (const_int 1)))]) (define_expand "atomic_test_and_set" [(match_operand:QI 0 "register_operand" "") @@ -307,5 +318,12 @@ UNSPECV_LDSTUB)) (set (match_dup 1) (const_int -1))] "!sparc_fix_ut699" - "ldstub\t%1, %0" - [(set_attr "type" "multi")]) +{ + if (sparc_fix_gr712rc) + return ".align\t16\n\tldstub\t%1, %0"; + else + return "ldstub\t%1, %0"; +} + [(set_attr "type" "multi") + (set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true") + (const_int 4) (const_int 1)))]) |