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| author | Wilco Dijkstra <wdijkstr@arm.com> | 2015-07-27 16:18:36 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2015-07-27 16:18:36 +0000 |
| commit | ad7b853a10903ecbf8ed945b855422a924181456 (patch) | |
| tree | fddd4fba8e1a219fae4f88898c629f84d5042e98 /gcc | |
| parent | 6d60b856e4228daa75ea3514bfcaf1664e2b56d3 (diff) | |
| download | gcc-ad7b853a10903ecbf8ed945b855422a924181456.zip gcc-ad7b853a10903ecbf8ed945b855422a924181456.tar.gz gcc-ad7b853a10903ecbf8ed945b855422a924181456.tar.bz2 | |
[PATCH][AArch64] Improve spill code - swap order in shr patterns
gcc/
* gcc/config/aarch64/aarch64.md (aarch64_lshr_sisd_or_int_<mode>3):
Place integer variant first.
(aarch64_ashr_sisd_or_int_<mode>3): Likewise.
From-SVN: r226253
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 27 |
2 files changed, 20 insertions, 13 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b7fca44..c27c20d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-07-27 Wilco Dijkstra <wdijkstr@arm.com> + + * gcc/config/aarch64/aarch64.md (aarch64_lshr_sisd_or_int_<mode>3): + Place integer variant first. + (aarch64_ashr_sisd_or_int_<mode>3): Likewise. + 2015-07-27 Alan Lawrence <alan.lawrence@arm.com> PR/63870 diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 65e4c66..01cdf9c 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3538,17 +3538,18 @@ ;; Logical right shift using SISD or Integer instruction (define_insn "*aarch64_lshr_sisd_or_int_<mode>3" - [(set (match_operand:GPI 0 "register_operand" "=w,&w,r") + [(set (match_operand:GPI 0 "register_operand" "=r,w,&w,&w") (lshiftrt:GPI - (match_operand:GPI 1 "register_operand" "w,w,r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "Us<cmode>,w,rUs<cmode>")))] + (match_operand:GPI 1 "register_operand" "r,w,w,w") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "rUs<cmode>,Us<cmode>,w,0")))] "" "@ + lsr\t%<w>0, %<w>1, %<w>2 ushr\t%<rtn>0<vas>, %<rtn>1<vas>, %2 # - lsr\t%<w>0, %<w>1, %<w>2" - [(set_attr "simd" "yes,yes,no") - (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,shift_reg")] + #" + [(set_attr "simd" "no,yes,yes,yes") + (set_attr "type" "shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")] ) (define_split @@ -3583,18 +3584,18 @@ ;; Arithmetic right shift using SISD or Integer instruction (define_insn "*aarch64_ashr_sisd_or_int_<mode>3" - [(set (match_operand:GPI 0 "register_operand" "=w,&w,&w,r") + [(set (match_operand:GPI 0 "register_operand" "=r,w,&w,&w") (ashiftrt:GPI - (match_operand:GPI 1 "register_operand" "w,w,w,r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_di" "Us<cmode>,w,0,rUs<cmode>")))] + (match_operand:GPI 1 "register_operand" "r,w,w,w") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_di" "rUs<cmode>,Us<cmode>,w,0")))] "" "@ + asr\t%<w>0, %<w>1, %<w>2 sshr\t%<rtn>0<vas>, %<rtn>1<vas>, %2 # - # - asr\t%<w>0, %<w>1, %<w>2" - [(set_attr "simd" "yes,yes,yes,no") - (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>,shift_reg")] + #" + [(set_attr "simd" "no,yes,yes,yes") + (set_attr "type" "shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")] ) (define_split |