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| author | Andreas Krebbel <krebbel@linux.vnet.ibm.com> | 2017-09-26 10:34:08 +0000 |
|---|---|---|
| committer | Andreas Krebbel <krebbel@gcc.gnu.org> | 2017-09-26 10:34:08 +0000 |
| commit | a55e2541cb4481e72c8e52564ad541b577489641 (patch) | |
| tree | 35d3343b1b017964c4d64e734999e2a512c25c17 /gcc | |
| parent | 252c6f56386b674a6fb9329d928269858a2cfe35 (diff) | |
| download | gcc-a55e2541cb4481e72c8e52564ad541b577489641.zip gcc-a55e2541cb4481e72c8e52564ad541b577489641.tar.gz gcc-a55e2541cb4481e72c8e52564ad541b577489641.tar.bz2 | |
S/390: Add FP vec_pack/unpack
gcc/ChangeLog:
2017-09-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/vector.md ("vec_unpacks_lo_v4sf")
("vec_unpacks_hi_v4sf", "vec_unpacks_lo_v2df")
("vec_unpacks_hi_v2df", "vec_pack_trunc_v2df"): New expanders.
From-SVN: r253194
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/s390/vector.md | 96 |
2 files changed, 101 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 71339e1..1de13a1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2017-09-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + * config/s390/vector.md ("vec_unpacks_lo_v4sf") + ("vec_unpacks_hi_v4sf", "vec_unpacks_lo_v2df") + ("vec_unpacks_hi_v2df", "vec_pack_trunc_v2df"): New expanders. + +2017-09-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com> + * config/s390/predicates.md ("const_shift_by_byte_operand"): New predicate. * config/s390/vector.md ("*vec_srb<mode>"): Change modes to V_128 diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index e61bb88..c15d81d 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -1781,7 +1781,7 @@ ;; vector load lengthened -; vflls +; vflls float -> double (define_insn "*vec_extendv4sf" [(set (match_operand:V2DF 0 "register_operand" "=v") (float_extend:V2DF @@ -1792,6 +1792,34 @@ "vldeb\t%v0,%v1" [(set_attr "op_type" "VRR")]) +(define_expand "vec_unpacks_lo_v4sf" + [(set (match_dup 2) + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") + (match_dup 1)] + UNSPEC_VEC_MERGEL)) + (set (match_operand:V2DF 0 "register_operand" "=v") + (float_extend:V2DF + (vec_select:V2SF + (match_dup 2) + (parallel [(const_int 0) (const_int 2)]))))] + "TARGET_VX" +{ operands[2] = gen_reg_rtx(V4SFmode); }) + +(define_expand "vec_unpacks_hi_v4sf" + [(set (match_dup 2) + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") + (match_dup 1)] + UNSPEC_VEC_MERGEH)) + (set (match_operand:V2DF 0 "register_operand" "=v") + (float_extend:V2DF + (vec_select:V2SF + (match_dup 2) + (parallel [(const_int 0) (const_int 2)]))))] + "TARGET_VX" +{ operands[2] = gen_reg_rtx(V4SFmode); }) + + +; double -> long double (define_insn "*vec_extendv2df" [(set (match_operand:V1TF 0 "register_operand" "=v") (float_extend:V1TF @@ -1802,6 +1830,72 @@ "wflld\t%v0,%v1" [(set_attr "op_type" "VRR")]) +(define_expand "vec_unpacks_lo_v2df" + [(set (match_dup 2) + (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "v") + (match_dup 1)] + UNSPEC_VEC_MERGEL)) + (set (match_operand:V1TF 0 "register_operand" "=v") + (float_extend:V1TF + (vec_select:V1DF + (match_dup 2) + (parallel [(const_int 0)]))))] + "TARGET_VXE" +{ operands[2] = gen_reg_rtx (V2DFmode); }) + +(define_expand "vec_unpacks_hi_v2df" + [(set (match_dup 2) + (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "v") + (match_dup 1)] + UNSPEC_VEC_MERGEH)) + (set (match_operand:V1TF 0 "register_operand" "=v") + (float_extend:V1TF + (vec_select:V1DF + (match_dup 2) + (parallel [(const_int 0)]))))] + "TARGET_VXE" +{ operands[2] = gen_reg_rtx (V2DFmode); }) + + +; 2 x v2df -> 1 x v4sf +(define_expand "vec_pack_trunc_v2df" + [(set (match_dup 3) + (unspec:V4SF [(match_operand:V2DF 1 "register_operand" "") + (const_int VEC_INEXACT) + (const_int VEC_RND_CURRENT)] + UNSPEC_VEC_VFLR)) + (set (match_dup 4) + (unspec:V4SF [(match_operand:V2DF 2 "register_operand" "") + (const_int VEC_INEXACT) + (const_int VEC_RND_CURRENT)] + UNSPEC_VEC_VFLR)) + (set (match_dup 6) + (unspec:V16QI [(subreg:V16QI (match_dup 3) 0) + (subreg:V16QI (match_dup 4) 0) + (match_dup 5)] + UNSPEC_VEC_PERM)) + (set (match_operand:V4SF 0 "register_operand" "") + (subreg:V4SF (match_dup 6) 0))] + "TARGET_VX" +{ + rtx constv, perm[16]; + int i; + + for (i = 0; i < 4; ++i) + { + perm[i] = GEN_INT (i); + perm[i + 4] = GEN_INT (i + 8); + perm[i + 8] = GEN_INT (i + 16); + perm[i + 12] = GEN_INT (i + 24); + } + constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)); + + operands[3] = gen_reg_rtx (V4SFmode); + operands[4] = gen_reg_rtx (V4SFmode); + operands[5] = force_reg (V16QImode, constv); + operands[6] = gen_reg_rtx (V16QImode); +}) + ; reduc_smin ; reduc_smax ; reduc_umin |