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| author | Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> | 2023-01-14 23:21:55 +0530 |
|---|---|---|
| committer | Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> | 2023-01-14 23:24:30 +0530 |
| commit | a3b99b84609af310c72b4d6221621f5b63a3c169 (patch) | |
| tree | 49bdd3dd9dcad1a6b8fff0b20cae0238196df0db /gcc | |
| parent | 9afc914809ca90d03a9a8f53c439ebf4c62cf544 (diff) | |
| download | gcc-a3b99b84609af310c72b4d6221621f5b63a3c169.zip gcc-a3b99b84609af310c72b4d6221621f5b63a3c169.tar.gz gcc-a3b99b84609af310c72b4d6221621f5b63a3c169.tar.bz2 | |
[aarch64] Fold ldr+dup to ld1rq for little endian targets.
gcc/ChangeLog:
* config/aarch64/aarch64-sve.md (aarch64_vec_duplicate_vq<mode>_le):
Change to define_insn_and_split to fold ldr+dup to ld1rq.
* config/aarch64/predicates.md (aarch64_sve_dup_ld1rq_operand): New.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/acle/general/pr96463-2.c: Adjust.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64-sve.md | 30 | ||||
| -rw-r--r-- | gcc/config/aarch64/predicates.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr96463-2.c | 3 |
3 files changed, 31 insertions, 6 deletions
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index b8cc47e..4548375 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -2533,14 +2533,34 @@ ) ;; Duplicate an Advanced SIMD vector to fill an SVE vector (LE version). -(define_insn "@aarch64_vec_duplicate_vq<mode>_le" - [(set (match_operand:SVE_FULL 0 "register_operand" "=w") + +(define_insn_and_split "@aarch64_vec_duplicate_vq<mode>_le" + [(set (match_operand:SVE_FULL 0 "register_operand" "=w, w") (vec_duplicate:SVE_FULL - (match_operand:<V128> 1 "register_operand" "w")))] + (match_operand:<V128> 1 "aarch64_sve_dup_ld1rq_operand" "w, UtQ"))) + (clobber (match_scratch:VNx16BI 2 "=X, Upl"))] "TARGET_SVE && !BYTES_BIG_ENDIAN" { - operands[1] = gen_rtx_REG (<MODE>mode, REGNO (operands[1])); - return "dup\t%0.q, %1.q[0]"; + switch (which_alternative) + { + case 0: + operands[1] = gen_rtx_REG (<MODE>mode, REGNO (operands[1])); + return "dup\t%0.q, %1.q[0]"; + case 1: + return "#"; + default: + gcc_unreachable (); + } + } + "&& MEM_P (operands[1])" + [(const_int 0)] + { + if (GET_CODE (operands[2]) == SCRATCH) + operands[2] = gen_reg_rtx (VNx16BImode); + emit_move_insn (operands[2], CONSTM1_RTX (VNx16BImode)); + rtx gp = gen_lowpart (<VPRED>mode, operands[2]); + emit_insn (gen_aarch64_sve_ld1rq<mode> (operands[0], operands[1], gp)); + DONE; } ) diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index ff7f73d..6062f37 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -676,6 +676,10 @@ (ior (match_operand 0 "register_operand") (match_operand 0 "aarch64_sve_ld1r_operand"))) +(define_predicate "aarch64_sve_dup_ld1rq_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "aarch64_sve_ld1rq_operand"))) + (define_predicate "aarch64_sve_ptrue_svpattern_immediate" (and (match_code "const") (match_test "aarch64_sve_ptrue_svpattern_p (op, NULL)"))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr96463-2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr96463-2.c index 196de3f..93daf23 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr96463-2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr96463-2.c @@ -26,4 +26,5 @@ TEST(svfloat64_t, float64_t, f64) TEST(svbfloat16_t, bfloat16_t, bf16) -/* { dg-final { scan-assembler-times {\tdup\tz[0-9]+\.q, z[0-9]+\.q\[0\]} 12 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-not {\tdup\t} } } */ +/* { dg-final { scan-assembler-times {\tld1rq} 12 } } */ |