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authorDaniel Cederman <cederman@gaisler.com>2015-09-28 05:26:34 +0000
committerDaniel Hellstrom <danielh@gcc.gnu.org>2015-09-28 07:26:34 +0200
commit9cb00eb15a97e52eff396db89cefac6a9297604f (patch)
treee019dafb4bb506b32cd7ed7d3a9f7b94e73e6798 /gcc
parent65629a24068d45300b73bc54faf3f02269e428ff (diff)
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Do not use floating point registers when compiling with -msoft-float for SPARC
2015-09-28 Daniel Cederman <cederman@gaisler.com> Do not use floating point registers when compiling with -msoft-float for SPARC __builtin_apply* and __builtin_return accesses the floating point registers on SPARC even when compiling with -msoft-float. gcc/ * config/sparc/sparc.c (sparc_function_value_regno_p): Do not return true on %f0 for a target without FPU. * config/sparc/sparc.md (untyped_call): Do not save %f0 for a target without FPU. (untyped_return): Do not load %f0 for a target without FPU. From-SVN: r228183
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog8
-rw-r--r--gcc/config/sparc/sparc.c2
-rw-r--r--gcc/config/sparc/sparc.md26
3 files changed, 25 insertions, 11 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index feca144..6eb3032 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2015-09-28 Daniel Cederman <cederman@gaisler.com>
+
+ * config/sparc/sparc.c (sparc_function_value_regno_p): Do not return
+ true on %f0 for a target without FPU.
+ * config/sparc/sparc.md (untyped_call): Do not save %f0 for a target
+ without FPU.
+ (untyped_return): Do not load %f0 for a target without FPU.
+
2015-09-28 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64.md (prefetch):
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index ed8a166..43f0170 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -7395,7 +7395,7 @@ sparc_libcall_value (machine_mode mode,
static bool
sparc_function_value_regno_p (const unsigned int regno)
{
- return (regno == 8 || regno == 32);
+ return (regno == 8 || (TARGET_FPU && regno == 32));
}
/* Do what is necessary for `va_start'. We look at the current function
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 5b9f051..e01db51 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -6398,7 +6398,6 @@
""
{
rtx valreg1 = gen_rtx_REG (DImode, 8);
- rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
rtx result = operands[1];
/* Pass constm1 to indicate that it may expect a structure value, but
@@ -6407,8 +6406,12 @@
/* Save the function value registers. */
emit_move_insn (adjust_address (result, DImode, 0), valreg1);
- emit_move_insn (adjust_address (result, TARGET_ARCH64 ? TFmode : DFmode, 8),
- valreg2);
+ if (TARGET_FPU)
+ {
+ rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
+ emit_move_insn (adjust_address (result, TARGET_ARCH64 ? TFmode : DFmode, 8),
+ valreg2);
+ }
/* The optimizer does not know that the call sets the function value
registers we stored in the result block. We avoid problems by
@@ -6620,7 +6623,6 @@
""
{
rtx valreg1 = gen_rtx_REG (DImode, 24);
- rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
rtx result = operands[0];
if (! TARGET_ARCH64)
@@ -6637,14 +6639,18 @@
emit_insn (gen_update_return (rtnreg, value));
}
- /* Reload the function value registers. */
+ /* Reload the function value registers.
+ Put USE insns before the return. */
emit_move_insn (valreg1, adjust_address (result, DImode, 0));
- emit_move_insn (valreg2,
- adjust_address (result, TARGET_ARCH64 ? TFmode : DFmode, 8));
-
- /* Put USE insns before the return. */
emit_use (valreg1);
- emit_use (valreg2);
+
+ if (TARGET_FPU)
+ {
+ rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
+ emit_move_insn (valreg2,
+ adjust_address (result, TARGET_ARCH64 ? TFmode : DFmode, 8));
+ emit_use (valreg2);
+ }
/* Construct the return. */
expand_naked_return ();