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authorVladimir Makarov <vmakarov@redhat.com>2014-06-13 20:28:10 +0000
committerVladimir Makarov <vmakarov@gcc.gnu.org>2014-06-13 20:28:10 +0000
commit9afb455c25fabe799656b446eaa4511169339aad (patch)
treea12f2f6f9dffc7b11511ffdc586964dff8accd59 /gcc
parent8241efd129cd9cfa6d474973e22aa073bfe05163 (diff)
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lra-assign.c (assign_by_spills): Add code to assign vector regs to inheritance pseudos.
2014-06-13 Vladimir Makarov <vmakarov@redhat.com> * lra-assign.c (assign_by_spills): Add code to assign vector regs to inheritance pseudos. * config/i386/i386.c (ix86_spill_class): Add check on NO_REGS. From-SVN: r211655
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog6
-rw-r--r--gcc/config/i386/i386.c2
-rw-r--r--gcc/lra-assigns.c25
3 files changed, 32 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 64046d4..edb3fc0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2014-06-13 Vladimir Makarov <vmakarov@redhat.com>
+
+ * lra-assign.c (assign_by_spills): Add code to assign vector regs
+ to inheritance pseudos.
+ * config/i386/i386.c (ix86_spill_class): Add check on NO_REGS.
+
2014-06-13 Peter Bergner <bergner@vnet.ibm.com>
PR target/61415
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 41f1b7f..c227b4a 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -46502,7 +46502,7 @@ ix86_spill_class (reg_class_t rclass, enum machine_mode mode)
{
if (TARGET_SSE && TARGET_GENERAL_REGS_SSE_SPILL && ! TARGET_MMX
&& (mode == SImode || (TARGET_64BIT && mode == DImode))
- && INTEGER_CLASS_P (rclass))
+ && rclass != NO_REGS && INTEGER_CLASS_P (rclass))
return ALL_SSE_REGS;
return NO_REGS;
}
diff --git a/gcc/lra-assigns.c b/gcc/lra-assigns.c
index 03c2506..cea4c33 100644
--- a/gcc/lra-assigns.c
+++ b/gcc/lra-assigns.c
@@ -1420,6 +1420,31 @@ assign_by_spills (void)
alternatives of insns containing the pseudo. */
bitmap_set_bit (&changed_pseudo_bitmap, regno);
}
+ else
+ {
+ enum reg_class rclass = lra_get_allocno_class (regno);
+ enum reg_class spill_class;
+
+ if (lra_reg_info[regno].restore_regno < 0
+ || ! bitmap_bit_p (&lra_inheritance_pseudos, regno)
+ || (spill_class
+ = ((enum reg_class)
+ targetm.spill_class
+ ((reg_class_t) rclass,
+ PSEUDO_REGNO_MODE (regno)))) == NO_REGS)
+ continue;
+ regno_allocno_class_array[regno] = spill_class;
+ hard_regno = find_hard_regno_for (regno, &cost, -1, false);
+ if (hard_regno < 0)
+ regno_allocno_class_array[regno] = rclass;
+ else
+ {
+ setup_reg_classes
+ (regno, spill_class, spill_class, spill_class);
+ assign_hard_regno (hard_regno, regno);
+ bitmap_set_bit (&changed_pseudo_bitmap, regno);
+ }
+ }
}
}
free (update_hard_regno_preference_check);