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| author | Bernd Schmidt <bernd.schmidt@analog.com> | 2006-12-08 12:42:44 +0000 |
|---|---|---|
| committer | Bernd Schmidt <bernds@gcc.gnu.org> | 2006-12-08 12:42:44 +0000 |
| commit | 96f46444e146883a2edbf66ba29a911e08e05037 (patch) | |
| tree | 1ae5ecb308b61fabc103e1bde34bdcf3bd241232 /gcc | |
| parent | 5fecd26633731c86f37ef89b40012ed6ca1daa6c (diff) | |
| download | gcc-96f46444e146883a2edbf66ba29a911e08e05037.zip gcc-96f46444e146883a2edbf66ba29a911e08e05037.tar.gz gcc-96f46444e146883a2edbf66ba29a911e08e05037.tar.bz2 | |
bfin.c (effective_address_32bit_p): Return true for anything involving the GOT.
* config/bfin/bfin.c (effective_address_32bit_p): Return true for
anything involving the GOT.
(bfin_adjust_cost): Don't take the REGNO of a MEM.
(trapping_loads_p): Look inside the pattern of an insn to find the
SET.
* config/bfin/bfin.md (attr "type"): Add movcc.
(insn_reservation "alu"): Likewise.
(movsicc_insn1, movsicc_insn2): Change type to movcc.
From-SVN: r119655
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 11 | ||||
| -rw-r--r-- | gcc/config/bfin/bfin.c | 12 | ||||
| -rw-r--r-- | gcc/config/bfin/bfin.md | 8 |
3 files changed, 24 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6a38e9d..998d8c9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2006-12-08 Bernd Schmidt <bernd.schmidt@analog.com> + + * config/bfin/bfin.c (effective_address_32bit_p): Return true for + anything involving the GOT. + (bfin_adjust_cost): Don't take the REGNO of a MEM. + (trapping_loads_p): Look inside the pattern of an insn to find the + SET. + * config/bfin/bfin.md (attr "type"): Add movcc. + (insn_reservation "alu"): Likewise. + (movsicc_insn1, movsicc_insn2): Change type to movcc. + 2006-12-07 Andrew Pinski <andrew_pinski@playstation.sony.com> * config/spu/spu-c.c (spu_build_overload_builtin): Delete. diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c index abfeaee..e31ced1 100644 --- a/gcc/config/bfin/bfin.c +++ b/gcc/config/bfin/bfin.c @@ -1097,6 +1097,9 @@ effective_address_32bit_p (rtx op, enum machine_mode mode) return 0; } + if (GET_CODE (XEXP (op, 1)) == UNSPEC) + return 1; + offset = INTVAL (XEXP (op, 1)); /* All byte loads use a 16 bit offset. */ @@ -2997,7 +3000,8 @@ bfin_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) rtx pat = PATTERN (dep_insn); rtx dest = SET_DEST (pat); rtx src = SET_SRC (pat); - if (! ADDRESS_REGNO_P (REGNO (dest)) || ! D_REGNO_P (REGNO (src))) + if (! ADDRESS_REGNO_P (REGNO (dest)) + || ! (MEM_P (src) || D_REGNO_P (REGNO (src)))) return cost; return cost + (dep_insn_type == TYPE_MOVE ? 4 : 3); } @@ -3918,10 +3922,12 @@ trapping_loads_p (rtx insn) { enum attr_type t; t = get_attr_type (XVECEXP (pat, 0, 1)); - if (t == TYPE_MCLD && may_trap_p (SET_SRC (XVECEXP (pat, 0, 1)))) + if (t == TYPE_MCLD + && may_trap_p (SET_SRC (PATTERN (XVECEXP (pat, 0, 1))))) return true; t = get_attr_type (XVECEXP (pat, 0, 2)); - if (t == TYPE_MCLD && may_trap_p (SET_SRC (XVECEXP (pat, 0, 2)))) + if (t == TYPE_MCLD + && may_trap_p (SET_SRC (PATTERN (XVECEXP (pat, 0, 2))))) return true; return false; } diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md index 4542327..8a59ce8 100644 --- a/gcc/config/bfin/bfin.md +++ b/gcc/config/bfin/bfin.md @@ -159,7 +159,7 @@ (MACFLAG_IH 10)]) (define_attr "type" - "move,mvi,mcld,mcst,dsp32,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy" + "move,movcc,mvi,mcld,mcst,dsp32,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy" (const_string "misc")) (define_attr "addrtype" "32bit,preg,ireg" @@ -198,7 +198,7 @@ (define_reservation "core" "slot0+slot1+slot2") (define_insn_reservation "alu" 1 - (eq_attr "type" "move,mvi,alu0,shft,brcc,br,call,misc,sync,compare") + (eq_attr "type" "move,movcc,mvi,alu0,shft,brcc,br,call,misc,sync,compare") "core") (define_insn_reservation "imul" 3 @@ -352,7 +352,7 @@ if cc %0 =%2; /* movsicc-1b */ if !cc %0 =%1; if cc %0=%2; /* movsicc-1 */" [(set_attr "length" "2,2,4") - (set_attr "type" "move") + (set_attr "type" "movcc") (set_attr "seq_insns" "*,*,multi")]) (define_insn "*movsicc_insn2" @@ -368,7 +368,7 @@ if cc %0 =%1; /* movsicc-2a */ if cc %0 =%1; if !cc %0=%2; /* movsicc-1 */" [(set_attr "length" "2,2,4") - (set_attr "type" "move") + (set_attr "type" "movcc") (set_attr "seq_insns" "*,*,multi")]) ;; Insns to load HIGH and LO_SUM |