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| author | liuhongt <hongtao.liu@intel.com> | 2023-08-25 08:46:26 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2023-08-28 09:25:48 +0800 |
| commit | 945217845db7edb499d66ac56480ce569002b83e (patch) | |
| tree | a8db7b9f388b395faaf03a64e179cabd877a3669 /gcc | |
| parent | e030af3e6f6d3ae555d6f70047ea3a2bf5744b7e (diff) | |
| download | gcc-945217845db7edb499d66ac56480ce569002b83e.zip gcc-945217845db7edb499d66ac56480ce569002b83e.tar.gz gcc-945217845db7edb499d66ac56480ce569002b83e.tar.bz2 | |
Use vmaskmov{ps,pd} for VI48_128_256 when TARGET_AVX2 is not available.
vpmaskmov{d,q} is available for TARGET_AVX2, vmaskmov{ps,ps} is
available for TARGET_AVX, w/o TARGET_AVX2, we can use vmaskmov{ps,pd}
for VI48_128_256
gcc/ChangeLog:
PR target/111119
* config/i386/sse.md (V48_AVX2): Rename to ..
(V48_128_256): .. this.
(ssefltmodesuffix): Extend to V4SF/V8SF/V2DF/V4DF.
(<avx_avx2>_maskload<ssemodesuffix><avxsizesuffix>): Change
V48_AVX2 to V48_128_256, also generate vmaskmov{ps,pd} for
integral modes when TARGET_AVX2 is not available.
(<avx_avx2>_maskstore<ssemodesuffix><avxsizesuffix>): Ditto.
(maskload<mode><sseintvecmodelower>): Change V48_AVX2 to
V48_128_256.
(maskstore<mode><sseintvecmodelower>): Ditto.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/sse.md | 48 |
1 files changed, 30 insertions, 18 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 4857545..192e746 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -693,11 +693,12 @@ [ (V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI (V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX") V8HI]) -(define_mode_iterator V48_AVX2 +(define_mode_iterator V48_128_256 [V4SF V2DF + V4DI V2DI V8SF V4DF - (V4SI "TARGET_AVX2") (V2DI "TARGET_AVX2") - (V8SI "TARGET_AVX2") (V4DI "TARGET_AVX2")]) + V8SI V4SI]) + (define_mode_iterator VF4_128_8_256 [V4DF V4SF]) @@ -22249,7 +22250,8 @@ (set_attr "mode" "<MODE>")]) (define_mode_attr ssefltmodesuffix - [(V2DI "pd") (V4DI "pd") (V4SI "ps") (V8SI "ps")]) + [(V2DI "pd") (V4DI "pd") (V4SI "ps") (V8SI "ps") + (V2DF "pd") (V4DF "pd") (V4SF "ps") (V8SF "ps")]) (define_mode_attr ssefltvecmode [(V2DI "V2DF") (V4DI "V4DF") (V4SI "V4SF") (V8SI "V8SF")]) @@ -27360,13 +27362,18 @@ (set_attr "mode" "OI")]) (define_insn "<avx_avx2>_maskload<ssemodesuffix><avxsizesuffix>" - [(set (match_operand:V48_AVX2 0 "register_operand" "=x") - (unspec:V48_AVX2 + [(set (match_operand:V48_128_256 0 "register_operand" "=x") + (unspec:V48_128_256 [(match_operand:<sseintvecmode> 2 "register_operand" "x") - (match_operand:V48_AVX2 1 "memory_operand" "m")] + (match_operand:V48_128_256 1 "memory_operand" "m")] UNSPEC_MASKMOV))] "TARGET_AVX" - "v<sseintprefix>maskmov<ssemodesuffix>\t{%1, %2, %0|%0, %2, %1}" +{ + if (TARGET_AVX2) + return "v<sseintprefix>maskmov<ssemodesuffix>\t{%1, %2, %0|%0, %2, %1}"; + else + return "vmaskmov<ssefltmodesuffix>\t{%1, %2, %0|%0, %2, %1}"; +} [(set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "prefix" "vex") @@ -27374,14 +27381,19 @@ (set_attr "mode" "<sseinsnmode>")]) (define_insn "<avx_avx2>_maskstore<ssemodesuffix><avxsizesuffix>" - [(set (match_operand:V48_AVX2 0 "memory_operand" "+m") - (unspec:V48_AVX2 + [(set (match_operand:V48_128_256 0 "memory_operand" "+m") + (unspec:V48_128_256 [(match_operand:<sseintvecmode> 1 "register_operand" "x") - (match_operand:V48_AVX2 2 "register_operand" "x") + (match_operand:V48_128_256 2 "register_operand" "x") (match_dup 0)] UNSPEC_MASKMOV))] "TARGET_AVX" - "v<sseintprefix>maskmov<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" +{ + if (TARGET_AVX2) + return "v<sseintprefix>maskmov<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"; + else + return "vmaskmov<ssefltmodesuffix>\t{%2, %1, %0|%0, %1, %2}"; +} [(set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "prefix" "vex") @@ -27389,10 +27401,10 @@ (set_attr "mode" "<sseinsnmode>")]) (define_expand "maskload<mode><sseintvecmodelower>" - [(set (match_operand:V48_AVX2 0 "register_operand") - (unspec:V48_AVX2 + [(set (match_operand:V48_128_256 0 "register_operand") + (unspec:V48_128_256 [(match_operand:<sseintvecmode> 2 "register_operand") - (match_operand:V48_AVX2 1 "memory_operand")] + (match_operand:V48_128_256 1 "memory_operand")] UNSPEC_MASKMOV))] "TARGET_AVX") @@ -27417,10 +27429,10 @@ "TARGET_AVX512BW") (define_expand "maskstore<mode><sseintvecmodelower>" - [(set (match_operand:V48_AVX2 0 "memory_operand") - (unspec:V48_AVX2 + [(set (match_operand:V48_128_256 0 "memory_operand") + (unspec:V48_128_256 [(match_operand:<sseintvecmode> 2 "register_operand") - (match_operand:V48_AVX2 1 "register_operand") + (match_operand:V48_128_256 1 "register_operand") (match_dup 0)] UNSPEC_MASKMOV))] "TARGET_AVX") |