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| author | Walter Lee <walt@tilera.com> | 2014-01-25 20:24:57 +0000 |
|---|---|---|
| committer | Walter Lee <walt@gcc.gnu.org> | 2014-01-25 20:24:57 +0000 |
| commit | 8e90a6255fdf3cb39dbd2e80fc8e7c091834b68b (patch) | |
| tree | 1f774bec111b57c238aaf4588c36a3d8c66ee3e1 /gcc | |
| parent | 450c1ffe7717b814b69154b2ab0f66239a8820ba (diff) | |
| download | gcc-8e90a6255fdf3cb39dbd2e80fc8e7c091834b68b.zip gcc-8e90a6255fdf3cb39dbd2e80fc8e7c091834b68b.tar.gz gcc-8e90a6255fdf3cb39dbd2e80fc8e7c091834b68b.tar.bz2 | |
tilegx.c (tilegx_gen_bundles): Delete barrier insns after bundles have been formed.
2014-01-25 Walter Lee <walt@tilera.com>
* config/tilegx/tilegx.c (tilegx_gen_bundles): Delete barrier
insns after bundles have been formed.
* config/tilegx/tilegx.md (tile_network_barrier): Update
comment.
From-SVN: r207081
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/tilegx/tilegx.c | 18 | ||||
| -rw-r--r-- | gcc/config/tilegx/tilegx.md | 6 |
3 files changed, 25 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a4f5fd5..36ec716a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2014-01-25 Walter Lee <walt@tilera.com> + * config/tilegx/tilegx.c (tilegx_gen_bundles): Delete barrier + insns before bundling. + * config/tilegx/tilegx.md (tile_network_barrier): Update + comment. + +2014-01-25 Walter Lee <walt@tilera.com> + * config/tilegx/tilegx.c (tilegx_expand_builtin): Set PREFETCH_SCHEDULE_BARRIER_P to true for prefetches. * config/tilepro/tilepro.c (tilepro_expand_builtin): Ditto. diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c index c168621..7694e31 100644 --- a/gcc/config/tilegx/tilegx.c +++ b/gcc/config/tilegx/tilegx.c @@ -4401,10 +4401,12 @@ tilegx_gen_bundles (void) basic_block bb; FOR_EACH_BB_FN (bb, cfun) { - rtx insn, next; + rtx insn, next, prev; rtx end = NEXT_INSN (BB_END (bb)); - for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn; insn = next) + prev = NULL_RTX; + for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn; + prev = insn, insn = next) { next = next_insn_to_bundle (NEXT_INSN (insn), end); @@ -4429,6 +4431,18 @@ tilegx_gen_bundles (void) PUT_MODE (insn, SImode); } } + + /* Delete barrier insns, because they can mess up the + emitting of bundle braces. If it is end-of-bundle, then + the previous insn must be marked end-of-bundle. */ + if (get_attr_type (insn) == TYPE_NOTHING) { + if (GET_MODE (insn) == QImode && prev != NULL + && GET_MODE (prev) == SImode) + { + PUT_MODE (prev, QImode); + } + delete_insn (insn); + } } } } diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md index 1e82abc..c8c7af6 100644 --- a/gcc/config/tilegx/tilegx.md +++ b/gcc/config/tilegx/tilegx.md @@ -5171,10 +5171,8 @@ ;; Network intrinsics -;; Note the "pseudo" text is handled specially by the -;; asm_output_opcode routine. If the output is an empty string, the -;; instruction would bypass the asm_output_opcode routine, bypassing -;; the bundle handling code. +;; Note the this barrier is of type "nothing," which is deleted after +;; the final scheduling pass so that nothing is emitted for it. (define_insn "tilegx_network_barrier" [(unspec_volatile:SI [(const_int 0)] UNSPEC_NETWORK_BARRIER)] "" |