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| author | DJ Delorie <dj@redhat.com> | 2006-03-10 12:49:02 -0500 |
|---|---|---|
| committer | DJ Delorie <dj@gcc.gnu.org> | 2006-03-10 12:49:02 -0500 |
| commit | 8e4edce73fe0d2001ed264da7af150f3d15f08af (patch) | |
| tree | 83cf7a3d9a11cd477ff1cc9d1b1fca7886840b63 /gcc | |
| parent | 891c0eeed7c8b2b087f908bd845ab0bea7663b00 (diff) | |
| download | gcc-8e4edce73fe0d2001ed264da7af150f3d15f08af.zip gcc-8e4edce73fe0d2001ed264da7af150f3d15f08af.tar.gz gcc-8e4edce73fe0d2001ed264da7af150f3d15f08af.tar.bz2 | |
m32c.c (m32c_const_ok_for_constraint_p): Bit numbers start at zero.
* config/m32c/m32c.c (m32c_const_ok_for_constraint_p): Bit numbers
start at zero.
(m32c_expand_insv): Fix test for an AND mask.
From-SVN: r111937
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/m32c/m32c.c | 14 |
2 files changed, 15 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 77ce19e..f7f45d2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2006-03-10 DJ Delorie <dj@redhat.com> + + * config/m32c/m32c.c (m32c_const_ok_for_constraint_p): Bit numbers + start at zero. + (m32c_expand_insv): Fix test for an AND mask. + 2006-03-10 Richard Guenther <rguenther@suse.de> PR middle-end/26565 diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c index 75fc3bc..0f7269b 100644 --- a/gcc/config/m32c/m32c.c +++ b/gcc/config/m32c/m32c.c @@ -923,22 +923,22 @@ m32c_const_ok_for_constraint_p (HOST_WIDE_INT value, if (memcmp (str, "Ilb", 3) == 0) { int b = exact_log2 (value); - return (b >= 1 && b <= 8); + return (b >= 0 && b <= 7); } if (memcmp (str, "Imb", 3) == 0) { int b = exact_log2 ((value ^ 0xff) & 0xff); - return (b >= 1 && b <= 8); + return (b >= 0 && b <= 7); } if (memcmp (str, "Ilw", 3) == 0) { int b = exact_log2 (value); - return (b >= 1 && b <= 16); + return (b >= 0 && b <= 15); } if (memcmp (str, "Imw", 3) == 0) { int b = exact_log2 ((value ^ 0xffff) & 0xffff); - return (b >= 1 && b <= 16); + return (b >= 0 && b <= 15); } if (memcmp (str, "I00", 3) == 0) { @@ -3455,13 +3455,17 @@ m32c_expand_insv (rtx *operands) mask >>= 8; } - if (INTVAL (operands[3])) + /* First, we generate a mask with the correct polarity. If we are + storing a zero, we want an AND mask, so invert it. */ + if (INTVAL (operands[3]) == 0) { if (GET_MODE (op0) == HImode) mask ^= 0xffff; else mask ^= 0xff; } + /* Now we need to properly sign-extend the mask in case we need to + fall back to an AND or OR opcode. */ if (GET_MODE (op0) == HImode) { if (mask & 0x8000) |