RISC-V: Add test for vec_duplicate + vnmsub.vv signed combine with GR2VR cost 0, 1 and 15

Add asm dump check and run test for vec_duplicate + vnmsub.vv
combine to vnmsub.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
	for vnmsub.vx.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h: Add test
	helper macros.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h: Add test
	data for run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

18 files changed, 446 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index 29cab3a..8879af3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index 0e7c967..1b7b740 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index 1524e71..00d8ef7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index 0967fc3..4480635 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index fd0098d..d02aaa3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index e73ef30..5921fe6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index ab4c6c2..3b53319 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index cb9c253..ca9fa4a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index 881917b..573ae91 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index e60e232..5fab6be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index 3aade3c..5d67e47 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index 3c7935d..d889a84 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -26,3 +26,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
index 06fde11..987aa73 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
@@ -49,10 +49,12 @@ test_vx_ternary_##NAME##_##T##_case_1 (T * restrict vd, T * restrict vs2, \
   DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc)                        \
   DEF_VX_TERNARY_CASE_1_WRAP(T, *, +, madd)                        \
   DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, nmsac)                       \
+  DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, nmsub)                       \
 
 #define TEST_TERNARY_VX_UNSIGNED_0(T)                              \
   DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc)                        \
   DEF_VX_TERNARY_CASE_1_WRAP(T, *, +, madd)                        \
   DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, nmsac)                       \
+  DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, nmsub)                       \
 
 #endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
index 447a58c..08c71fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
@@ -1110,4 +1110,372 @@ uint64_t TEST_TERNARY_DATA(uint64_t, madd)[][4][N] =
   },
 };
 
+int8_t TEST_TERNARY_DATA(int8_t, nmsub)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+    },
+  },
+  {
+    { 127 }, /* rs1 */
+    { /* vs2 */
+       127,  127,  127,  127,
+         2,    2,    2,    2,
+         0,    0,    0,    0,
+      -128, -128, -128, -128,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    {
+       127,  127,  127,  127,
+      -125, -125, -125, -125,
+        -8,   -8,   -8,   -8,
+       126,  126,  126,  126,
+    },
+  },
+};
+
+int16_t TEST_TERNARY_DATA(int16_t, nmsub)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+    },
+  },
+  {
+    { 32767 }, /* rs1 */
+    { /* vs2 */
+       32767,  32767,  32767,  32767,
+           2,      2,      2,      2,
+           0,      0,      0,      0,
+      -32768, -32768, -32768, -32768,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    {
+       32767,  32767,  32767,  32767,
+      -32765, -32765, -32765, -32765,
+          -8,     -8,     -8,     -8,
+       32766,  32766,  32766,  32766,
+    },
+  },
+};
+
+int32_t TEST_TERNARY_DATA(int32_t, nmsub)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+    },
+  },
+  {
+    { 2147483647 }, /* rs1 */
+    { /* vs2 */
+       2147483647,  2147483647,  2147483647,  2147483647,
+                2,           2,           2,           2,
+                0,           0,           0,           0,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+      -2147483645, -2147483645, -2147483645, -2147483645,
+               -8,          -8,          -8,          -8,
+       2147483646,  2147483646,  2147483646,  2147483646,
+    },
+  },
+};
+
+int64_t TEST_TERNARY_DATA(int64_t, nmsub)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+    },
+  },
+  {
+    { 9223372036854775807ull }, /* rs1 */
+    { /* vs2 */
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+                            2,                       2,                       2,                       2,
+                            0,                       0,                       0,                       0,
+      -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    {
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+      -9223372036854775805ull, -9223372036854775805ull, -9223372036854775805ull, -9223372036854775805ull,
+                           -8,                      -8,                      -8,                      -8,
+       9223372036854775806ull,  9223372036854775806ull,  9223372036854775806ull,  9223372036854775806ull,
+    },
+  },
+};
+
+uint8_t TEST_TERNARY_DATA(uint8_t, nmsub)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       8,  8,  8,  8,
+       7,  7,  7,  7,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       7,  7,  7,  7,
+       5,  5,  5,  5,
+    },
+  },
+  {
+    { 128 }, /* rs1 */
+    { /* vs2 */
+       127,  127,  127,  127,
+       255,  255,  255,  255,
+       254,  254,  254,  254,
+       252,  252,  252,  252,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       8,  8,  8,  8,
+       2,  2,  2,  2,
+    },
+    {
+       127,  127,  127,  127,
+       127,  127,  127,  127,
+       254,  254,  254,  254,
+       252,  252,  252,  252,
+    },
+  },
+};
+
+uint16_t TEST_TERNARY_DATA(uint16_t, nmsub)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       8,  8,  8,  8,
+       7,  7,  7,  7,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       7,  7,  7,  7,
+       5,  5,  5,  5,
+    },
+  },
+  {
+    { 32768 }, /* rs1 */
+    { /* vs2 */
+       32767,  32767,  32767,  32767,
+       65535,  65535,  65535,  65535,
+       65534,  65534,  65534,  65534,
+       65532,  65532,  65532,  65532,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       8,  8,  8,  8,
+       2,  2,  2,  2,
+    },
+    {
+       32767,  32767,  32767,  32767,
+       32767,  32767,  32767,  32767,
+       65534,  65534,  65534,  65534,
+       65532,  65532,  65532,  65532,
+    },
+  },
+};
+
+uint32_t TEST_TERNARY_DATA(uint32_t, nmsub)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       8,  8,  8,  8,
+       7,  7,  7,  7,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       7,  7,  7,  7,
+       5,  5,  5,  5,
+    },
+  },
+  {
+    { 2147483648 }, /* rs1 */
+    { /* vs2 */
+       2147483647,  2147483647,  2147483647,  2147483647,
+       4294967295,  4294967295,  4294967295,  4294967295,
+       4294967294,  4294967294,  4294967294,  4294967294,
+       4294967292,  4294967292,  4294967292,  4294967292,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       8,  8,  8,  8,
+       2,  2,  2,  2,
+    },
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+       2147483647,  2147483647,  2147483647,  2147483647,
+       4294967294,  4294967294,  4294967294,  4294967294,
+       4294967292,  4294967292,  4294967292,  4294967292,
+    },
+  },
+};
+
+uint64_t TEST_TERNARY_DATA(uint64_t, nmsub)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       8,  8,  8,  8,
+       7,  7,  7,  7,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       7,  7,  7,  7,
+       5,  5,  5,  5,
+    },
+  },
+  {
+    { 9223372036854775808ull }, /* rs1 */
+    { /* vs2 */
+        9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,
+       18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,
+       18446744073709551614ull,  18446744073709551614ull,  18446744073709551614ull,  18446744073709551614ull,
+       18446744073709551612ull,  18446744073709551612ull,  18446744073709551612ull,  18446744073709551612ull,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       8,  8,  8,  8,
+       2,  2,  2,  2,
+    },
+    {
+        9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,
+        9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,
+       18446744073709551614ull,  18446744073709551614ull,  18446744073709551614ull,  18446744073709551614ull,
+       18446744073709551612ull,  18446744073709551612ull,  18446744073709551612ull,  18446744073709551612ull,
+    },
+  },
+};
+
 #endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i16.c
new file mode 100644
index 0000000..5d0c33a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int16_t
+#define NAME       nmsub
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i32.c
new file mode 100644
index 0000000..e7cd272
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int32_t
+#define NAME       nmsub
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i64.c
new file mode 100644
index 0000000..c038e5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int64_t
+#define NAME       nmsub
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i8.c
new file mode 100644
index 0000000..52325b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i8.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int8_t
+#define NAME       nmsub
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"