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| author | Haochen Jiang <haochen.jiang@intel.com> | 2023-10-09 16:10:03 +0800 |
|---|---|---|
| committer | Haochen Jiang <haochen.jiang@intel.com> | 2023-10-09 17:09:09 +0800 |
| commit | 85bd47bf4b0fb82e5c9b12952324ea3e5f94c50a (patch) | |
| tree | a17d751db942a157684799a4c2e92e07fc1cd172 /gcc | |
| parent | 43b08ab2fad8f399febbad1d24cd7ddb9fc5a6d5 (diff) | |
| download | gcc-85bd47bf4b0fb82e5c9b12952324ea3e5f94c50a.zip gcc-85bd47bf4b0fb82e5c9b12952324ea3e5f94c50a.tar.gz gcc-85bd47bf4b0fb82e5c9b12952324ea3e5f94c50a.tar.bz2 | |
Allow -mno-evex512 usage
gcc/ChangeLog:
* config/i386/i386.opt: Allow -mno-evex512.
gcc/testsuite/ChangeLog:
* gcc.target/i386/noevex512-1.c: New test.
* gcc.target/i386/noevex512-2.c: Ditto.
* gcc.target/i386/noevex512-3.c: Ditto.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/i386.opt | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/noevex512-1.c | 13 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/noevex512-2.c | 13 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/noevex512-3.c | 13 |
4 files changed, 40 insertions, 1 deletions
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index b5029b4..05ba7f3 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1342,5 +1342,5 @@ Enable GPR32 in inline asm when APX_EGPR enabled, do not hook reg or mem constraint in inline asm to GPR16. mevex512 -Target RejectNegative Mask(ISA2_EVEX512) Var(ix86_isa_flags2) Save +Target Mask(ISA2_EVEX512) Var(ix86_isa_flags2) Save Support 512 bit vector built-in functions and code generation. diff --git a/gcc/testsuite/gcc.target/i386/noevex512-1.c b/gcc/testsuite/gcc.target/i386/noevex512-1.c new file mode 100644 index 0000000..7fd45f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/noevex512-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -march=x86-64 -mavx512f -mno-evex512 -Wno-psabi" } */ +/* { dg-final { scan-assembler-not ".%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__m512d +foo () +{ + __m512d a, b; + a = a + b; + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/noevex512-2.c b/gcc/testsuite/gcc.target/i386/noevex512-2.c new file mode 100644 index 0000000..1c206e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/noevex512-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -mavx512bw -mno-evex512" } */ + +#include <immintrin.h> + +long long +foo (long long c) +{ + register long long a __asm ("k7") = c; + long long b = foo (a); + asm volatile ("" : "+k" (b)); /* { dg-error "inconsistent operand constraints in an 'asm'" } */ + return b; +} diff --git a/gcc/testsuite/gcc.target/i386/noevex512-3.c b/gcc/testsuite/gcc.target/i386/noevex512-3.c new file mode 100644 index 0000000..10e00c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/noevex512-3.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -Wno-psabi -mavx512f" } */ +/* { dg-final { scan-assembler-not ".%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__attribute__ ((target ("no-evex512"))) __m512d +foo () +{ + __m512d a, b; + a = a + b; + return a; +} |