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| author | Richard Henderson <rth@redhat.com> | 2011-01-11 10:28:59 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 2011-01-11 10:28:59 -0800 |
| commit | 85a337b58a1a6088d085354aa28de8b5198e8d08 (patch) | |
| tree | 7deed119e939b6f57b15932b9e0d854c7e425658 /gcc | |
| parent | a5c727e3babe7dfdb78652074dcefbedb10ab1a0 (diff) | |
| download | gcc-85a337b58a1a6088d085354aa28de8b5198e8d08.zip gcc-85a337b58a1a6088d085354aa28de8b5198e8d08.tar.gz gcc-85a337b58a1a6088d085354aa28de8b5198e8d08.tar.bz2 | |
mn10300: Define the A and D constraints.
This will allow combining am33 and mn103 alternatives
without having to resort to the enabled attribute.
The existing 'A' constraint renamed to 'c'. Thankfully
this existing accumulator constraint doesn't appear in
either newlib or eglibc sources.
From-SVN: r168675
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/mn10300/constraints.md | 11 | ||||
| -rw-r--r-- | gcc/config/mn10300/mn10300.md | 8 |
3 files changed, 19 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8d5fb42..5b290b7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2011-01-11 Richard Henderson <rth@redhat.com> + * config/mn10300/constraints.md ("c"): Rename from "A". + ("A", "D"): New constraint letters. + * config/mn10300/mn10300.md (fmasf4): Use the "c" constraint. + (fmssf4, fnmasf4, fnmssf4): Likewise. + * config/mn10300/mn10300.md (isa): New attribute. (enabled): New attribute. diff --git a/gcc/config/mn10300/constraints.md b/gcc/config/mn10300/constraints.md index 509970c..c9863fc 100644 --- a/gcc/config/mn10300/constraints.md +++ b/gcc/config/mn10300/constraints.md @@ -23,6 +23,15 @@ (define_register_constraint "a" "ADDRESS_REGS" "An address register.") +;; This can be used for QI/HImode memory operations, and most arithmetic. +;; AM33 supports these on all registers, where MN103 needs DATA_REGS. +(define_register_constraint "D" "TARGET_AM33 ? GENERAL_REGS : DATA_REGS" + "A general register for AM33, and a data register otherwise.") + +;; Similarly for ADDRESS_REGS vs GENERAL_REGS. +(define_register_constraint "A" "TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS" + "A general register for AM33, and an address register otherwise.") + (define_register_constraint "y" "SP_REGS" "An SP register (if available).") @@ -32,7 +41,7 @@ (define_register_constraint "f" "TARGET_AM33_2 ? FP_REGS : NO_REGS" "A floating point register.") -(define_register_constraint "A" "TARGET_AM33_2 ? FP_ACC_REGS : NO_REGS" +(define_register_constraint "c" "TARGET_AM33_2 ? FP_ACC_REGS : NO_REGS" "A floating point accumulator register.") (define_memory_constraint "Q" diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md index bfa453f..1773a03 100644 --- a/gcc/config/mn10300/mn10300.md +++ b/gcc/config/mn10300/mn10300.md @@ -2717,7 +2717,7 @@ ) (define_insn "fmasf4" - [(set (match_operand:SF 0 "register_operand" "=A") + [(set (match_operand:SF 0 "register_operand" "=c") (fma:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f") (match_operand:SF 3 "register_operand" "f"))) @@ -2730,7 +2730,7 @@ ) (define_insn "fmssf4" - [(set (match_operand:SF 0 "register_operand" "=A") + [(set (match_operand:SF 0 "register_operand" "=c") (fma:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f") (neg:SF (match_operand:SF 3 "register_operand" "f")))) @@ -2743,7 +2743,7 @@ ) (define_insn "fnmasf4" - [(set (match_operand:SF 0 "register_operand" "=A") + [(set (match_operand:SF 0 "register_operand" "=c") (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f")) (match_operand:SF 2 "register_operand" "f") (match_operand:SF 3 "register_operand" "f"))) @@ -2756,7 +2756,7 @@ ) (define_insn "fnmssf4" - [(set (match_operand:SF 0 "register_operand" "=A") + [(set (match_operand:SF 0 "register_operand" "=c") (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f")) (match_operand:SF 2 "register_operand" "f") (neg:SF (match_operand:SF 3 "register_operand" "f")))) |