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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2015-04-21 11:24:05 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2015-04-21 11:24:05 +0000 |
| commit | 8409e468a5f94b7577ccfa073f8b859481a86800 (patch) | |
| tree | 6e942a7bac25815b14a048ec7298994c9c07d87d /gcc | |
| parent | 8a29fdfd2313cde40aad2dcabe3ddc4d2aca0f91 (diff) | |
| download | gcc-8409e468a5f94b7577ccfa073f8b859481a86800.zip gcc-8409e468a5f94b7577ccfa073f8b859481a86800.tar.gz gcc-8409e468a5f94b7577ccfa073f8b859481a86800.tar.bz2 | |
[AArch64] Add zero_extend variants of logical+not ops
* config/aarch64/aarch64.md (*<NLOGICAL:optab>_one_cmplsidi3_ze):
New pattern.
(*xor_one_cmplsidi3_ze): Likewise.
From-SVN: r222263
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 20 |
2 files changed, 26 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 73ede9e..2a982b1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-04-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64.md (*<NLOGICAL:optab>_one_cmplsidi3_ze): + New pattern. + (*xor_one_cmplsidi3_ze): Likewise. + 2015-04-21 Thomas Preud'homme <thomas.preudhomme@arm.com> * df-core.c (df_finish_pass): Iterate over df->problems_by_index[] and diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 534a862..429c5ba 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3058,6 +3058,26 @@ (set_attr "simd" "*,yes")] ) +(define_insn "*<NLOGICAL:optab>_one_cmplsidi3_ze" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (NLOGICAL:SI (not:SI (match_operand:SI 1 "register_operand" "r")) + (match_operand:SI 2 "register_operand" "r"))))] + "" + "<NLOGICAL:nlogical>\\t%w0, %w2, %w1" + [(set_attr "type" "logic_reg")] +) + +(define_insn "*xor_one_cmplsidi3_ze" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (not:SI (xor:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")))))] + "" + "eon\\t%w0, %w1, %w2" + [(set_attr "type" "logic_reg")] +) + ;; (xor (not a) b) is simplify_rtx-ed down to (not (xor a b)). ;; eon does not operate on SIMD registers so the vector variant must be split. (define_insn_and_split "*xor_one_cmpl<mode>3" |