diff options
| author | Dongyan Chen <chendongyan@isrc.iscas.ac.cn> | 2025-05-06 17:09:54 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2025-05-06 17:09:54 -0600 |
| commit | 82126b26d17ed2c5ee48ca51e3fed69e898c9a20 (patch) | |
| tree | 87f39691f3fb2ca5855fbff3e97b9760a90f688d /gcc | |
| parent | aed2a447c7ff4282621aa7941f840cb2ddc90354 (diff) | |
| download | gcc-82126b26d17ed2c5ee48ca51e3fed69e898c9a20.zip gcc-82126b26d17ed2c5ee48ca51e3fed69e898c9a20.tar.gz gcc-82126b26d17ed2c5ee48ca51e3fed69e898c9a20.tar.bz2 | |
[PATCH] RISC-V: Minimal support for sdtrig and ssstrict extensions.
This patch support sdtrig and ssstrict extensions[1].
To enable GCC to recognize and process sdtrig and ssstrict extensions correctly
at compile time.
[1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extension.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-47.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/common/config/riscv/riscv-common.cc | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/arch-47.c | 5 |
2 files changed, 8 insertions, 0 deletions
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 58c7d20..0233e1a 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -432,6 +432,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0}, {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0}, + {"sdtrig", ISA_SPEC_CLASS_NONE, 1, 0}, + {"smaia", ISA_SPEC_CLASS_NONE, 1, 0}, {"smepmp", ISA_SPEC_CLASS_NONE, 1, 0}, {"smstateen", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -440,6 +442,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"sscofpmf", ISA_SPEC_CLASS_NONE, 1, 0}, {"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0}, {"sstc", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ssstrict", ISA_SPEC_CLASS_NONE, 1, 0}, {"svade", ISA_SPEC_CLASS_NONE, 1, 0}, {"svadu", ISA_SPEC_CLASS_NONE, 1, 0}, diff --git a/gcc/testsuite/gcc.target/riscv/arch-47.c b/gcc/testsuite/gcc.target/riscv/arch-47.c new file mode 100644 index 0000000..06bc80f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-47.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_sdtrig_ssstrict -mabi=lp64" } */ +int foo() +{ +} |