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| author | Richard Sandiford <richard.sandiford@arm.com> | 2022-02-03 10:44:00 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2022-02-03 10:44:00 +0000 |
| commit | 7e4f89a23e32604f71f8f6756c8856bf07bf7ac2 (patch) | |
| tree | ed93c9ad662aac4ca6cea855a66105e359ac3646 /gcc | |
| parent | 6a770526600a7ffda1f288fa481a4322d5f149b4 (diff) | |
| download | gcc-7e4f89a23e32604f71f8f6756c8856bf07bf7ac2.zip gcc-7e4f89a23e32604f71f8f6756c8856bf07bf7ac2.tar.gz gcc-7e4f89a23e32604f71f8f6756c8856bf07bf7ac2.tar.bz2 | |
aarch64: Add missing movmisalign patterns
The Advanced SIMD movmisalign patterns didn't handle 16-bit
FP modes, which meant that the vector loop for:
void
test (_Float16 *data)
{
_Pragma ("omp simd")
for (int i = 0; i < 8; ++i)
data[i] = 1.0;
}
would be versioned for alignment.
This was causing some new failures in aarch64/sve/single_5.c:
FAIL: gcc.target/aarch64/sve/single_5.c scan-assembler-not \\tb
FAIL: gcc.target/aarch64/sve/single_5.c scan-assembler-not \\tcmp
FAIL: gcc.target/aarch64/sve/single_5.c scan-assembler-times \\tstr\\tq[0-9]+, 10
but I didn't look into what changed from earlier releases.
Adding the missing modes removes some existing xfails.
gcc/
* config/aarch64/aarch64-simd.md (movmisalign<mode>): Extend from
VALL to VALL_F16.
gcc/testsuite/
* gcc.target/aarch64/sve/single_5.c: Remove some XFAILs.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/single_5.c | 7 |
2 files changed, 5 insertions, 6 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index f6d7b42..6646e06 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -50,8 +50,8 @@ ) (define_expand "movmisalign<mode>" - [(set (match_operand:VALL 0 "nonimmediate_operand") - (match_operand:VALL 1 "general_operand"))] + [(set (match_operand:VALL_F16 0 "nonimmediate_operand") + (match_operand:VALL_F16 1 "general_operand"))] "TARGET_SIMD && !STRICT_ALIGNMENT" { /* This pattern is not permitted to fail during expansion: if both arguments diff --git a/gcc/testsuite/gcc.target/aarch64/sve/single_5.c b/gcc/testsuite/gcc.target/aarch64/sve/single_5.c index 7d16205..233118b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/single_5.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/single_5.c @@ -13,15 +13,14 @@ /* { dg-final { scan-assembler-times {\tmovi\tv[0-9]+\.4s, 0x6\n} 1 } } */ /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #7\n} 1 { xfail *-*-* } } } */ /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #8\n} 1 { xfail *-*-* } } } */ -/* { dg-final { scan-assembler-times {\tfmov\tv[0-9]+\.8h, 1\.0e\+0\n} 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tfmov\tv[0-9]+\.8h, 1\.0e\+0\n} 1 } } */ /* { dg-final { scan-assembler-times {\tfmov\tv[0-9]+\.4s, 2\.0e\+0\n} 1 } } */ /* { dg-final { scan-assembler-times {\tfmov\tv[0-9]+\.2d, 3\.0e\+0\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tstr\tq[0-9]+,} 11 { xfail *-*-* } } } */ -/* { dg-final { scan-assembler-times {\tstr\tq[0-9]+,} 10 } } */ +/* { dg-final { scan-assembler-times {\tstr\tq[0-9]+,} 11 } } */ /* { dg-final { scan-assembler-not {\twhile} } } */ /* { dg-final { scan-assembler-not {\tb} } } */ /* { dg-final { scan-assembler-not {\tcmp} } } */ /* { dg-final { scan-assembler-not {\tindex} } } */ -/* { dg-final { scan-assembler-not {\tptrue\t} { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-not {\tptrue\t} } } */ |