diff options
author | liuhongt <hongtao.liu@intel.com> | 2024-09-23 11:06:04 +0800 |
---|---|---|
committer | liuhongt <hongtao.liu@intel.com> | 2024-09-26 09:42:15 +0800 |
commit | 78eef8919e2f2973ed7750ba66f5726e70614d07 (patch) | |
tree | 8f99626aec0d1ae62ce9f7a5f8cdc6b5e6724c18 /gcc | |
parent | 064d5c67d7ad2be446c19e84f0cd993ecab784c3 (diff) | |
download | gcc-78eef8919e2f2973ed7750ba66f5726e70614d07.zip gcc-78eef8919e2f2973ed7750ba66f5726e70614d07.tar.gz gcc-78eef8919e2f2973ed7750ba66f5726e70614d07.tar.bz2 |
Define VECTOR_STORE_FLAG_VALUE
gcc/ChangeLog:
* config/i386/i386.h (VECTOR_STORE_FLAG_VALUE): New macro.
gcc/testsuite/ChangeLog:
* gcc.dg/rtl/x86_64/vector_eq.c: New test.
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/config/i386/i386.h | 5 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c | 26 |
2 files changed, 30 insertions, 1 deletions
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 751c250..58e6f28 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -899,7 +899,10 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); and give entire struct the alignment of an int. */ /* Required on the 386 since it doesn't have bit-field insns. */ #define PCC_BITFIELD_TYPE_MATTERS 1 - + +#define VECTOR_STORE_FLAG_VALUE(MODE) \ + (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT ? constm1_rtx : NULL_RTX) + /* Standard register usage. */ /* This processor has special stack-like registers. See reg-stack.cc diff --git a/gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c b/gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c new file mode 100644 index 0000000..6704c28 --- /dev/null +++ b/gcc/testsuite/gcc.dg/rtl/x86_64/vector_eq.c @@ -0,0 +1,26 @@ +/* { dg-do compile { target { { i?86-*-* x86_64-*-* } && lp64 } } } */ +/* { dg-additional-options "-O2 -march=x86-64-v3" } */ + +typedef int v4si __attribute__((vector_size(16))); + +v4si __RTL (startwith ("vregs")) foo (void) +{ +(function "foo" + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 1 [bb 2] NOTE_INSN_BASIC_BLOCK) + (cnote 2 NOTE_INSN_FUNCTION_BEG) + (cinsn 3 (set (reg:V4SI <0>) (const_vector:V4SI [(const_int 0) (const_int 0) (const_int 0) (const_int 0)]))) + (cinsn 5 (set (reg:V4SI <2>) + (eq:V4SI (reg:V4SI <0>) (reg:V4SI <1>)))) + (cinsn 6 (set (reg:V4SI <3>) (reg:V4SI <2>))) + (cinsn 7 (set (reg:V4SI xmm0) (reg:V4SI <3>))) + (edge-to exit (flags "FALLTHRU")) + ) + ) + (crtl (return_rtx (reg/i:V4SI xmm0))) +) +} + +/* { dg-final { scan-assembler-not "vpxor" } } */ |