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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2018-06-01 15:50:18 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2018-06-01 15:50:18 +0000 |
| commit | 77b8fb05b3ae9223abb7bac05d8af6892cfa251a (patch) | |
| tree | 78d710facd7d9b41c56e3ec05bb671c79726df82 /gcc | |
| parent | 7aad7f4b8508e26248205c2b408186b5f8f71ce5 (diff) | |
| download | gcc-77b8fb05b3ae9223abb7bac05d8af6892cfa251a.zip gcc-77b8fb05b3ae9223abb7bac05d8af6892cfa251a.tar.gz gcc-77b8fb05b3ae9223abb7bac05d8af6892cfa251a.tar.bz2 | |
[AArch64] Used prefer aliases SXTL(2) and UXTL(2)
The SSHL and USHL instructions are used with a shift operand of zero to
sign and zero-extend integer vectors into wider modes.
GCC makes extensive use of them to "unpack" vectors.
AArch64 defines a shorthand alias for that case. Instead of writing:
SSHLL <Vd>.<Ta>, <Vn>.<Tb>, 0
we can write
SXTL <Vd>.<Ta>, <Vn>.<Tb>
Similar for the unsigned versions and the high-part versions (SSHL2 -> SXTL2).
This makes the assembly of vectorised functions a bit more readable.
* config/aarch64/aarch64-simd.md
(aarch64_simd_vec_unpack<su>_lo_<mode>): Use UXTL and SXTL assembler
mnemonics.
(aarch64_simd_vec_unpack<su>_hi_<mode>): Use UXTL2 and SXTL2 assembler
mnemonics.
From-SVN: r261073
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 4 |
2 files changed, 10 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 87305ae..24cf22e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2018-06-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64-simd.md + (aarch64_simd_vec_unpack<su>_lo_<mode>): Use UXTL and SXTL assembler + mnemonics. + (aarch64_simd_vec_unpack<su>_hi_<mode>): Use UXTL2 and SXTL2 assembler + mnemonics. + 2018-06-01 Richard Sandiford <richard.sandiford@linaro.org> PR tree-optimization/85989 diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 4e5c42b..dc4e026 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1492,7 +1492,7 @@ (match_operand:VQW 2 "vect_par_cnst_lo_half" "") )))] "TARGET_SIMD" - "<su>shll\t%0.<Vwtype>, %1.<Vhalftype>, 0" + "<su>xtl\t%0.<Vwtype>, %1.<Vhalftype>" [(set_attr "type" "neon_shift_imm_long")] ) @@ -1503,7 +1503,7 @@ (match_operand:VQW 2 "vect_par_cnst_hi_half" "") )))] "TARGET_SIMD" - "<su>shll2\t%0.<Vwtype>, %1.<Vtype>, 0" + "<su>xtl2\t%0.<Vwtype>, %1.<Vtype>" [(set_attr "type" "neon_shift_imm_long")] ) |