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| author | Sudi Das <sudi.das@arm.com> | 2020-09-18 16:30:11 +0100 |
|---|---|---|
| committer | Omar Tahir <omar.tahir@arm.com> | 2020-09-18 17:04:37 +0100 |
| commit | 778f19ff953792702c0a7e1fde00214709d9317e (patch) | |
| tree | c290b5dd4f036105dd3cfe60ea7a61b075af22c7 /gcc | |
| parent | c2bb84be4a6e581bbf45891457ee632a07416982 (diff) | |
| download | gcc-778f19ff953792702c0a7e1fde00214709d9317e.zip gcc-778f19ff953792702c0a7e1fde00214709d9317e.tar.gz gcc-778f19ff953792702c0a7e1fde00214709d9317e.tar.bz2 | |
[PATCH 3/5][Arm] New pattern for CSINC instructions
This patch adds a new pattern, *thumb2_csinc, for generating CSINC
instructions. It also modifies an existing pattern, *thumb2_cond_arith, to
output CINC when the operation is an addition and TARGET_COND_ARITH is true.
gcc/ChangeLog:
* config/arm/thumb2.md (*thumb2_csinc): New.
(*thumb2_cond_arith): Generate CINC where possible.
gcc/testsuite/ChangeLog:
* gcc.target/arm/csinc-1.c: New test.
Co-authored-by: Omar Tahir <omar.tahir@arm.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/arm/thumb2.md | 19 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/csinc-1.c | 23 |
2 files changed, 42 insertions, 0 deletions
diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index d648ba1..0ff5a53 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -744,6 +744,10 @@ return \"%i5\\t%0, %1, %2, lsr #31\"; output_asm_insn (\"cmp\\t%2, %3\", operands); + + if (GET_CODE (operands[5]) == PLUS && TARGET_COND_ARITH) + return \"cinc\\t%0, %1, %d4\"; + if (GET_CODE (operands[5]) == AND) { output_asm_insn (\"ite\\t%D4\", operands); @@ -952,6 +956,21 @@ (set_attr "predicable" "no")] ) +(define_insn "*thumb2_csinc" + [(set (match_operand:SI 0 "arm_general_register_operand" "=r, r") + (if_then_else:SI + (match_operand 1 "arm_comparison_operation" "") + (plus:SI (match_operand:SI 2 "arm_general_register_operand" "r, r") + (const_int 1)) + (match_operand:SI 3 "reg_or_zero_operand" "r, Pz")))] + "TARGET_COND_ARITH" + "@ + csinc\\t%0, %3, %2, %D1 + csinc\\t%0, zr, %2, %D1" + [(set_attr "type" "csel") + (set_attr "predicable" "no")] +) + (define_insn "*thumb2_movcond" [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts,Ts") (if_then_else:SI diff --git a/gcc/testsuite/gcc.target/arm/csinc-1.c b/gcc/testsuite/gcc.target/arm/csinc-1.c new file mode 100644 index 0000000..b992849 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/csinc-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8_1m_main_ok } */ +/* { dg-options "-O2 -march=armv8.1-m.main" } */ + +int +test_csinc32_condasn1(int w0, int w1, int w2, int w3) +{ + int w4; + + /* { dg-final { scan-assembler "csinc\tr\[0-9\]*.*ne" } } */ + w4 = (w0 == w1) ? (w2 + 1) : w3; + return w4; +} + +int +test_csinc32_condasn2(int w0, int w1, int w2, int w3) +{ + int w4; + + /* { dg-final { scan-assembler "csinc\tr\[0-9\]*.*eq" } } */ + w4 = (w0 == w1) ? w3 : (w2 + 1); + return w4; +} |