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| author | Robin Dapp <rdapp@ventanamicro.com> | 2025-04-01 21:17:54 +0200 |
|---|---|---|
| committer | Robin Dapp <rdapp@ventanamicro.com> | 2025-04-02 21:41:18 +0200 |
| commit | 716d39f0a248c1003033e6a312c736180790ef70 (patch) | |
| tree | 837b798cf59c0a8441e8b01791cb0e9ce5a376e9 /gcc | |
| parent | dd6ebc0a3473a830115995bdcaf8f797ebd085a3 (diff) | |
| download | gcc-716d39f0a248c1003033e6a312c736180790ef70.zip gcc-716d39f0a248c1003033e6a312c736180790ef70.tar.gz gcc-716d39f0a248c1003033e6a312c736180790ef70.tar.bz2 | |
RISC-V: Fix vec_duplicate[bimode] expander [PR119572].
Since r15-9062-g70391e3958db79 we perform vector bitmask initialization
via the vec_duplicate expander directly. This triggered a latent bug in
ours where we missed to mask out the single bit which resulted in an
execution FAIL of pr119114.c
The attached patch adds the 1-masking of the broadcast operand.
PR target/119572
gcc/ChangeLog:
* config/riscv/autovec.md: Mask broadcast value.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/autovec.md | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index f53ed3a..9e51e3c 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -330,7 +330,15 @@ { poly_int64 nunits = GET_MODE_NUNITS (<MODE>mode); machine_mode mode = riscv_vector::get_vector_mode (QImode, nunits).require (); - rtx dup = expand_vector_broadcast (mode, operands[1]); + + /* The 1-bit mask is in a QImode register, make sure we only use the last + bit. See also PR119114 and the respective vec_init expander. */ + rtx tmp = gen_reg_rtx (Xmode); + emit_insn + (gen_rtx_SET (tmp, gen_rtx_AND (Xmode, gen_lowpart (Xmode, operands[1]), + CONST1_RTX (Xmode)))); + + rtx dup = expand_vector_broadcast (mode, gen_lowpart (QImode, tmp)); riscv_vector::expand_vec_cmp (operands[0], NE, dup, CONST0_RTX (mode)); DONE; } |