RISC-V: generate builtin macro for compilation with strict alignment

Distinguish between explicit -mstrict-align and cpu tune param
for slow_unaligned_access=true/false.

Tested for regressions using rv32/64 multilib with newlib/linux

gcc/ChangeLog:

	* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Generate
	__riscv_unaligned_avoid with value 1 or
	__riscv_unaligned_slow with value 1 or
	__riscv_unaligned_fast with value 1
	* config/riscv/riscv.cc (riscv_option_override): Define
	riscv_user_wants_strict_align. Set
	riscv_user_wants_strict_align to TARGET_STRICT_ALIGN
	* config/riscv/riscv.h: Declare riscv_user_wants_strict_align

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/attribute-1.c: Check for
	__riscv_unaligned_slow or __riscv_unaligned_fast
	* gcc.target/riscv/attribute-4.c: Check for
	__riscv_unaligned_avoid
	* gcc.target/riscv/attribute-5.c: Check for
	__riscv_unaligned_slow or __riscv_unaligned_fast
	* gcc.target/riscv/predef-align-1.c: New test.
	* gcc.target/riscv/predef-align-2.c: New test.
	* gcc.target/riscv/predef-align-3.c: New test.
	* gcc.target/riscv/predef-align-4.c: New test.
	* gcc.target/riscv/predef-align-5.c: New test.
	* gcc.target/riscv/predef-align-6.c: New test.

Reviewed-by: Jeff Law <jlaw@ventanamicro.com>
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
Co-authored-by: Vineet Gupta <vineetg@rivosinc.com>

12 files changed, 144 insertions, 0 deletions

diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 2937c16..283052a 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -108,6 +108,13 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
 
     }
 
+  if (riscv_user_wants_strict_align)
+    builtin_define_with_int_value ("__riscv_unaligned_avoid", 1);
+  else if (riscv_slow_unaligned_access_p)
+    builtin_define_with_int_value ("__riscv_unaligned_slow", 1);
+  else
+    builtin_define_with_int_value ("__riscv_unaligned_fast", 1);
+
   if (TARGET_MIN_VLEN != 0)
     builtin_define_with_int_value ("__riscv_v_min_vlen", TARGET_MIN_VLEN);
 
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index bab6ed7..db53857 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -248,6 +248,9 @@ struct riscv_tune_info {
 /* Whether unaligned accesses execute very slowly.  */
 bool riscv_slow_unaligned_access_p;
 
+/* Whether user explicitly passed -mstrict-align.  */
+bool riscv_user_wants_strict_align;
+
 /* Stack alignment to assume/maintain.  */
 unsigned riscv_stack_boundary;
 
@@ -7180,6 +7183,12 @@ riscv_option_override (void)
      -m[no-]strict-align is left unspecified, heed -mtune's advice.  */
   riscv_slow_unaligned_access_p = (cpu->tune_param->slow_unaligned_access
 				   || TARGET_STRICT_ALIGN);
+
+  /* Make a note if user explicity passed -mstrict-align for later
+     builtin macro generation.  Can't use target_flags_explicitly since
+     it is set even for -mno-strict-align.  */
+  riscv_user_wants_strict_align = TARGET_STRICT_ALIGN;
+
   if ((target_flags_explicit & MASK_STRICT_ALIGN) == 0
       && cpu->tune_param->slow_unaligned_access)
     target_flags |= MASK_STRICT_ALIGN;
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index e18a008..e093db0 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1036,6 +1036,7 @@ while (0)
 #ifndef USED_FOR_TARGET
 extern const enum reg_class riscv_regno_to_class[];
 extern bool riscv_slow_unaligned_access_p;
+extern bool riscv_user_wants_strict_align;
 extern unsigned riscv_stack_boundary;
 extern unsigned riscv_bytes_per_vector_chunk;
 extern poly_uint16 riscv_vector_chunks;
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-1.c b/gcc/testsuite/gcc.target/riscv/attribute-1.c
index bc919c5..abfb0b4 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-1.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-1.c
@@ -2,5 +2,17 @@
 /* { dg-options "-mriscv-attribute" } */
 int foo()
 {
+
+/* In absence of -m[no-]strict-align, default mcpu is currently 
+   set to rocket.  rocket has slow_unaligned_access=true.  */
+#if !defined(__riscv_unaligned_slow)
+#error "__riscv_unaligned_slow is not set"
+#endif
+
+#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast)
+#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set"
+#endif
+
+return 0;
 }
 /* { dg-final { scan-assembler ".attribute arch" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-4.c b/gcc/testsuite/gcc.target/riscv/attribute-4.c
index 7c565c4..545f87c 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-4.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-4.c
@@ -2,5 +2,15 @@
 /* { dg-options "-mriscv-attribute -mstrict-align" } */
 int foo()
 {
+
+#if !defined(__riscv_unaligned_avoid)
+#error "__riscv_unaligned_avoid is not set"
+#endif
+
+#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow)
+#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly set"
+#endif
+
+  return 0;
 }
 /* { dg-final { scan-assembler ".attribute unaligned_access, 0" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-5.c b/gcc/testsuite/gcc.target/riscv/attribute-5.c
index ee9cf69..753043c 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-5.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-5.c
@@ -2,5 +2,16 @@
 /* { dg-options "-mriscv-attribute -mno-strict-align" } */
 int foo()
 {
+
+/* Default mcpu is rocket which has slow_unaligned_access=true.  */
+#if !defined(__riscv_unaligned_slow)
+#error "__riscv_unaligned_slow is not set"
+#endif
+
+#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast)
+#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set"
+#endif
+
+return 0;
 }
 /* { dg-final { scan-assembler ".attribute unaligned_access, 1" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-1.c b/gcc/testsuite/gcc.target/riscv/predef-align-1.c
new file mode 100644
index 0000000..9dde37a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-align-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mtune=thead-c906" } */
+
+int main() {
+
+/* thead-c906 default is cpu tune param unaligned access fast */
+#if !defined(__riscv_unaligned_fast)
+#error "__riscv_unaligned_fast is not set"
+#endif
+
+#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_slow)
+#error "__riscv_unaligned_avoid or __riscv_unaligned_slow is unexpectedly set"
+#endif
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-2.c b/gcc/testsuite/gcc.target/riscv/predef-align-2.c
new file mode 100644
index 0000000..33d604f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-align-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mtune=thead-c906 -mstrict-align" } */
+
+int main() {
+
+#if !defined(__riscv_unaligned_avoid)
+#error "__riscv_unaligned_avoid is not set"
+#endif
+
+#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow)
+#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly set"
+#endif
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-3.c b/gcc/testsuite/gcc.target/riscv/predef-align-3.c
new file mode 100644
index 0000000..daf5718
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-align-3.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mtune=thead-c906 -mno-strict-align" } */
+
+int main() {
+
+/* thead-c906 default is cpu tune param unaligned access fast */
+#if !defined(__riscv_unaligned_fast)
+#error "__riscv_unaligned_fast is not set"
+#endif
+
+#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_slow)
+#error "__riscv_unaligned_avoid or __riscv_unaligned_slow is unexpectedly set"
+#endif
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-4.c b/gcc/testsuite/gcc.target/riscv/predef-align-4.c
new file mode 100644
index 0000000..d46a46f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-align-4.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mtune=rocket" } */
+
+int main() {
+
+/* rocket default is cpu tune param unaligned access slow */
+#if !defined(__riscv_unaligned_slow)
+#error "__riscv_unaligned_slow is not set"
+#endif
+
+#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast)
+#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set"
+#endif
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-5.c b/gcc/testsuite/gcc.target/riscv/predef-align-5.c
new file mode 100644
index 0000000..3aa25f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-align-5.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mtune=rocket -mstrict-align" } */
+
+int main() {
+
+#if !defined(__riscv_unaligned_avoid)
+#error "__riscv_unaligned_avoid is not set"
+#endif
+
+#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow)
+#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly set"
+#endif
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-6.c b/gcc/testsuite/gcc.target/riscv/predef-align-6.c
new file mode 100644
index 0000000..cb64d7e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-align-6.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mtune=rocket -mno-strict-align" } */
+
+int main() {
+
+/* rocket default is cpu tune param unaligned access slow */
+#if !defined(__riscv_unaligned_slow)
+#error "__riscv_unaligned_slow is not set"
+#endif
+
+#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast)
+#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set"
+#endif
+
+  return 0;
+}