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author | Uros Bizjak <ubizjak@gmail.com> | 2008-04-10 19:58:54 +0200 |
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committer | Uros Bizjak <uros@gcc.gnu.org> | 2008-04-10 19:58:54 +0200 |
commit | 6dd18eb1fe4255c5497ffe0d4731941910dd1391 (patch) | |
tree | 02aca4ab3be3403e3a6aaea00d67621f37a960d7 /gcc | |
parent | f40bee312d7d356e884bb7bcd94912b805cd21d0 (diff) | |
download | gcc-6dd18eb1fe4255c5497ffe0d4731941910dd1391.zip gcc-6dd18eb1fe4255c5497ffe0d4731941910dd1391.tar.gz gcc-6dd18eb1fe4255c5497ffe0d4731941910dd1391.tar.bz2 |
i386.md (absneg): New code iterator.
* config/i386/i386.md (absneg): New code iterator.
(absnegprefix): New code attribute.
(<code><mode>2): Macroize expander from abs<mode>2 and neg<mode>2
patterns using absneg code iterator.
(<code>tf2): Macroize expander from abstf2 and negtf2 patterns
using absneg code iterator.
(*<code><mode>2_1): Macroize insn pattern from *abs<mode>2_1 and
*neg<mode>2 patterns using absneg code iterator.
(*<code>extendsfdf2): Macroize insn pattern from *absextendsfdf2 and
*negextendsfdf2 patterns using absneg code iterator.
(*<code>extendsfxf2): Macroize insn pattern from *absextendsfxf2 and
*negextendsfxf2 patterns using absneg code iterator.
(*<code>extendsfdf2): Macroize insn pattern from *absextendsfdf2 and
*negextendsfdf2 patterns using absneg code iterator.
* config/i386/sse.md (<code><mode>2): Macroize expander from
abs<mode>2 and neg<mode>2 patterns using absneg code iterator.
From-SVN: r134165
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 19 | ||||
-rw-r--r-- | gcc/config/i386/i386.md | 102 | ||||
-rw-r--r-- | gcc/config/i386/sse.md | 19 |
3 files changed, 58 insertions, 82 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c2763ca..d9f60c8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,22 @@ +2008-04-10 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md (absneg): New code iterator. + (absnegprefix): New code attribute. + (<code><mode>2): Macroize expander from abs<mode>2 and neg<mode>2 + patterns using absneg code iterator. + (<code>tf2): Macroize expander from abstf2 and negtf2 patterns + using absneg code iterator. + (*<code><mode>2_1): Macroize insn pattern from *abs<mode>2_1 and + *neg<mode>2 patterns using absneg code iterator. + (*<code>extendsfdf2): Macroize insn pattern from *absextendsfdf2 and + *negextendsfdf2 patterns using absneg code iterator. + (*<code>extendsfxf2): Macroize insn pattern from *absextendsfxf2 and + *negextendsfxf2 patterns using absneg code iterator. + (*<code>extendsfdf2): Macroize insn pattern from *absextendsfdf2 and + *negextendsfdf2 patterns using absneg code iterator. + * config/i386/sse.md (<code><mode>2): Macroize expander from + abs<mode>2 and neg<mode>2 patterns using absneg code iterator. + 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com> * config/s390/s390.h: Remove the remains of the recent search diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 10f172e..d428c3b 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -548,7 +548,8 @@ (define_code_iterator umaxmin [umax umin]) ;; Base name for integer and FP insn mnemonic -(define_code_attr maxminiprefix [(smax "maxs") (smin "mins") (umax "maxu") (umin "minu")]) +(define_code_attr maxminiprefix [(smax "maxs") (smin "mins") + (umax "maxu") (umin "minu")]) (define_code_attr maxminfprefix [(smax "max") (smin "min")]) ;; Mapping of parallel logic operators @@ -557,6 +558,12 @@ ;; Base name for insn mnemonic. (define_code_attr plogicprefix [(and "and") (ior "or") (xor "xor")]) +;; Mapping of abs neg operators +(define_code_iterator absneg [abs neg]) + +;; Base name for x87 insn mnemonic. +(define_code_attr absnegprefix [(abs "abs") (neg "chs")]) + ;; All single word integer modes. (define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")]) @@ -10379,17 +10386,11 @@ ;; Changing of sign for FP values is doable using integer unit too. -(define_expand "neg<mode>2" +(define_expand "<code><mode>2" [(set (match_operand:X87MODEF 0 "register_operand" "") - (neg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))] + (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))] "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" - "ix86_expand_fp_absneg_operator (NEG, <MODE>mode, operands); DONE;") - -(define_expand "abs<mode>2" - [(set (match_operand:X87MODEF 0 "register_operand" "") - (abs:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))] - "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" - "ix86_expand_fp_absneg_operator (ABS, <MODE>mode, operands); DONE;") + "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;") (define_insn "*absneg<mode>2_mixed" [(set (match_operand:MODEF 0 "register_operand" "=x,x,f,!r") @@ -10418,17 +10419,11 @@ "TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" "#") -(define_expand "negtf2" - [(set (match_operand:TF 0 "register_operand" "") - (neg:TF (match_operand:TF 1 "register_operand" "")))] - "TARGET_64BIT" - "ix86_expand_fp_absneg_operator (NEG, TFmode, operands); DONE;") - -(define_expand "abstf2" +(define_expand "<code>tf2" [(set (match_operand:TF 0 "register_operand" "") - (abs:TF (match_operand:TF 1 "register_operand" "")))] + (absneg:TF (match_operand:TF 1 "register_operand" "")))] "TARGET_64BIT" - "ix86_expand_fp_absneg_operator (ABS, TFmode, operands); DONE;") + "ix86_expand_fp_absneg_operator (<CODE>, TFmode, operands); DONE;") (define_insn "*absnegtf2_sse" [(set (match_operand:TF 0 "register_operand" "=x,x") @@ -10568,75 +10563,40 @@ ;; Conditionalize these after reload. If they match before reload, we ;; lose the clobber and ability to use integer instructions. -(define_insn "*neg<mode>2_1" +(define_insn "*<code><mode>2_1" [(set (match_operand:X87MODEF 0 "register_operand" "=f") - (neg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))] + (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))] "TARGET_80387 - && (reload_completed || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))" - "fchs" + && (reload_completed + || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))" + "f<absnegprefix>" [(set_attr "type" "fsgn") (set_attr "mode" "<MODE>")]) -(define_insn "*abs<mode>2_1" - [(set (match_operand:X87MODEF 0 "register_operand" "=f") - (abs:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))] - "TARGET_80387 - && (reload_completed || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))" - "fabs" - [(set_attr "type" "fsgn") - (set_attr "mode" "<MODE>")]) - -(define_insn "*negextendsfdf2" - [(set (match_operand:DF 0 "register_operand" "=f") - (neg:DF (float_extend:DF - (match_operand:SF 1 "register_operand" "0"))))] - "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)" - "fchs" - [(set_attr "type" "fsgn") - (set_attr "mode" "DF")]) - -(define_insn "*negextenddfxf2" - [(set (match_operand:XF 0 "register_operand" "=f") - (neg:XF (float_extend:XF - (match_operand:DF 1 "register_operand" "0"))))] - "TARGET_80387" - "fchs" - [(set_attr "type" "fsgn") - (set_attr "mode" "XF")]) - -(define_insn "*negextendsfxf2" - [(set (match_operand:XF 0 "register_operand" "=f") - (neg:XF (float_extend:XF - (match_operand:SF 1 "register_operand" "0"))))] - "TARGET_80387" - "fchs" - [(set_attr "type" "fsgn") - (set_attr "mode" "XF")]) - -(define_insn "*absextendsfdf2" +(define_insn "*<code>extendsfdf2" [(set (match_operand:DF 0 "register_operand" "=f") - (abs:DF (float_extend:DF - (match_operand:SF 1 "register_operand" "0"))))] + (absneg:DF (float_extend:DF + (match_operand:SF 1 "register_operand" "0"))))] "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)" - "fabs" + "f<absnegprefix>" [(set_attr "type" "fsgn") (set_attr "mode" "DF")]) -(define_insn "*absextenddfxf2" +(define_insn "*<code>extendsfxf2" [(set (match_operand:XF 0 "register_operand" "=f") - (abs:XF (float_extend:XF - (match_operand:DF 1 "register_operand" "0"))))] + (absneg:XF (float_extend:XF + (match_operand:SF 1 "register_operand" "0"))))] "TARGET_80387" - "fabs" + "f<absnegprefix>" [(set_attr "type" "fsgn") (set_attr "mode" "XF")]) -(define_insn "*absextendsfxf2" +(define_insn "*<code>extenddfxf2" [(set (match_operand:XF 0 "register_operand" "=f") - (abs:XF (float_extend:XF - (match_operand:SF 1 "register_operand" "0"))))] + (absneg:XF (float_extend:XF + (match_operand:DF 1 "register_operand" "0"))))] "TARGET_80387" - "fabs" + "f<absnegprefix>" [(set_attr "type" "fsgn") (set_attr "mode" "XF")]) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e40416b..40ab297 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -43,8 +43,10 @@ (define_mode_attr ssevecsize [(V16QI "b") (V8HI "w") (V4SI "d") (V2DI "q")]) ;; Mapping of the sse5 suffix -(define_mode_attr ssemodesuffixf4 [(SF "ss") (DF "sd") (V4SF "ps") (V2DF "pd")]) -(define_mode_attr ssemodesuffixf2s [(SF "ss") (DF "sd") (V4SF "ss") (V2DF "sd")]) +(define_mode_attr ssemodesuffixf4 [(SF "ss") (DF "sd") + (V4SF "ps") (V2DF "pd")]) +(define_mode_attr ssemodesuffixf2s [(SF "ss") (DF "sd") + (V4SF "ss") (V2DF "sd")]) (define_mode_attr ssemodesuffixf2c [(V4SF "s") (V2DF "d")]) ;; Mapping of the max integer size for sse5 rotate immediate constraint @@ -346,17 +348,12 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_expand "neg<mode>2" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "") - (neg:SSEMODEF2P (match_operand:SSEMODEF2P 1 "register_operand" "")))] - "SSE_VEC_FLOAT_MODE_P (<MODE>mode)" - "ix86_expand_fp_absneg_operator (NEG, <MODE>mode, operands); DONE;") - -(define_expand "abs<mode>2" +(define_expand "<code><mode>2" [(set (match_operand:SSEMODEF2P 0 "register_operand" "") - (abs:SSEMODEF2P (match_operand:SSEMODEF2P 1 "register_operand" "")))] + (absneg:SSEMODEF2P + (match_operand:SSEMODEF2P 1 "register_operand" "")))] "SSE_VEC_FLOAT_MODE_P (<MODE>mode)" - "ix86_expand_fp_absneg_operator (ABS, <MODE>mode, operands); DONE;") + "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;") (define_expand "<addsub><mode>3" [(set (match_operand:SSEMODEF2P 0 "register_operand" "") |