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| author | Matthew Wahab <matthew.wahab@arm.com> | 2015-09-22 09:30:51 +0000 |
|---|---|---|
| committer | Matthew Wahab <mwahab@gcc.gnu.org> | 2015-09-22 09:30:51 +0000 |
| commit | 6380d2bc38237e00e3d460882b4b0938bbb068b9 (patch) | |
| tree | d0305b2f9a791ff2b65e8b1048998c498ad3e3ce /gcc | |
| parent | cc05c2c3e0d90c1a116a1a8cbdbc4d25f8062ea7 (diff) | |
| download | gcc-6380d2bc38237e00e3d460882b4b0938bbb068b9.zip gcc-6380d2bc38237e00e3d460882b4b0938bbb068b9.tar.gz gcc-6380d2bc38237e00e3d460882b4b0938bbb068b9.tar.bz2 | |
[AArch64] Add atomic load-operate instructions.
2015-09-22 Matthew Wahab <matthew.wahab@arm.com>
* config/aarch64/aarch64/atomics.md (UNSPECV_ATOMIC_LDOP): New.
(UNSPECV_ATOMIC_LDOP_OR): New.
(UNSPECV_ATOMIC_LDOP_BIC): New.
(UNSPECV_ATOMIC_LDOP_XOR): New.
(UNSPECV_ATOMIC_LDOP_PLUS): New.
(ATOMIC_LDOP): New.
(atomic_ldop): New.
(aarch64_atomic_load<atomic_ldop><mode>): New.
From-SVN: r228000
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 11 | ||||
| -rw-r--r-- | gcc/config/aarch64/atomics.md | 41 |
2 files changed, 52 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 568d1d7..27e773b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,16 @@ 2015-09-22 Matthew Wahab <matthew.wahab@arm.com> + * config/aarch64/aarch64/atomics.md (UNSPECV_ATOMIC_LDOP): New. + (UNSPECV_ATOMIC_LDOP_OR): New. + (UNSPECV_ATOMIC_LDOP_BIC): New. + (UNSPECV_ATOMIC_LDOP_XOR): New. + (UNSPECV_ATOMIC_LDOP_PLUS): New. + (ATOMIC_LDOP): New. + (atomic_ldop): New. + (aarch64_atomic_load<atomic_ldop><mode>): New. + +2015-09-22 Matthew Wahab <matthew.wahab@arm.com> + * config/aarch64/aarch64.md (<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3): Make a named pattern. diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index cb80539..11a9d13 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -29,8 +29,25 @@ UNSPECV_ATOMIC_CAS ; Represent an atomic CAS. UNSPECV_ATOMIC_SWP ; Represent an atomic SWP. UNSPECV_ATOMIC_OP ; Represent an atomic operation. + UNSPECV_ATOMIC_LDOP ; Represent an atomic load-operation + UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or + UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic + UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor + UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add ]) +;; Iterators for load-operate instructions. + +(define_int_iterator ATOMIC_LDOP + [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC + UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS]) + +(define_int_attr atomic_ldop + [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr") + (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")]) + +;; Instruction patterns. + (define_expand "atomic_compare_and_swap<mode>" [(match_operand:SI 0 "register_operand" "") ;; bool out (match_operand:ALLI 1 "register_operand" "") ;; val out @@ -536,3 +553,27 @@ else return "casal<atomic_sfx>\t%<w>0, %<w>2, %1"; }) + +;; Atomic load-op: Load data, operate, store result, keep data. + +(define_insn "aarch64_atomic_load<atomic_ldop><mode>" + [(set (match_operand:ALLI 0 "register_operand" "=r") + (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")) + (set (match_dup 1) + (unspec_volatile:ALLI + [(match_dup 1) + (match_operand:ALLI 2 "register_operand") + (match_operand:SI 3 "const_int_operand")] + ATOMIC_LDOP))] + "TARGET_LSE && reload_completed" + { + enum memmodel model = memmodel_from_int (INTVAL (operands[3])); + if (is_mm_relaxed (model)) + return "ld<atomic_ldop><atomic_sfx>\t%<w>2, %<w>0, %1"; + else if (is_mm_acquire (model) || is_mm_consume (model)) + return "ld<atomic_ldop>a<atomic_sfx>\t%<w>2, %<w>0, %1"; + else if (is_mm_release (model)) + return "ld<atomic_ldop>l<atomic_sfx>\t%<w>2, %<w>0, %1"; + else + return "ld<atomic_ldop>al<atomic_sfx>\t%<w>2, %<w>0, %1"; + }) |