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| author | Alan Lawrence <alan.lawrence@arm.com> | 2015-09-15 13:16:58 +0000 |
|---|---|---|
| committer | Alan Lawrence <alalaw01@gcc.gnu.org> | 2015-09-15 13:16:58 +0000 |
| commit | 635e66fec3addc5af7e2ab65793af7237e555922 (patch) | |
| tree | a36477036f51b2283384f554965e11a741eaa284 /gcc | |
| parent | 97755701afbdc34215954008d6550065631ca826 (diff) | |
| download | gcc-635e66fec3addc5af7e2ab65793af7237e555922.zip gcc-635e66fec3addc5af7e2ab65793af7237e555922.tar.gz gcc-635e66fec3addc5af7e2ab65793af7237e555922.tar.bz2 | |
[AArch64 array_mode 8/8] Add d-registers to TARGET_ARRAY_MODE_SUPPORTED_P
gcc/:
* config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): New.
* config/aarch64/aarch64.c (aarch64_array_mode_supported_p): Add
AARCH64_VALID_SIMD_DREG_MODE.
gcc/testsuite/:
* gcc.target/aarch64/vect_int32x2x4_1.c: New.
From-SVN: r227794
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 3 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.h | 6 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/vect_int32x2x4_1.c | 22 |
5 files changed, 41 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a4911a0..38719b9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2015-09-15 Alan Lawrence <alan.lawrence@arm.com> + * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): New. + + * config/aarch64/aarch64.c (aarch64_array_mode_supported_p): Add + AARCH64_VALID_SIMD_DREG_MODE. + +2015-09-15 Alan Lawrence <alan.lawrence@arm.com> + * config/aarch64/aarch64-simd.md (aarch64_ld2r<mode>, aarch64_ld3r<mode>, aarch64_ld4r<mode>): Combine together, making... (aarch64_simd_ld<VSTRUCT:nregs>r<VALLDIF:mode>): ...this. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 9c5cf4c..bbac271 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -677,7 +677,8 @@ aarch64_array_mode_supported_p (machine_mode mode, unsigned HOST_WIDE_INT nelems) { if (TARGET_SIMD - && AARCH64_VALID_SIMD_QREG_MODE (mode) + && (AARCH64_VALID_SIMD_QREG_MODE (mode) + || AARCH64_VALID_SIMD_DREG_MODE (mode)) && (nelems >= 2 && nelems <= 4)) return true; diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 9669e01..5a8db76 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -872,6 +872,12 @@ extern enum aarch64_code_model aarch64_cmodel; (aarch64_cmodel == AARCH64_CMODEL_TINY \ || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) +/* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register. */ +#define AARCH64_VALID_SIMD_DREG_MODE(MODE) \ + ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ + || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \ + || (MODE) == DFmode) + /* Modes valid for AdvSIMD Q registers. */ #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \ ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2355856..6cea108 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2015-09-15 Alan Lawrence <alan.lawrence@arm.com> + + * gcc.target/aarch64/vect_int32x2x4_1.c: New. + 2015-09-15 Richard Biener <rguenther@suse.de> PR middle-end/67563 diff --git a/gcc/testsuite/gcc.target/aarch64/vect_int32x2x4_1.c b/gcc/testsuite/gcc.target/aarch64/vect_int32x2x4_1.c new file mode 100644 index 0000000..734cfd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect_int32x2x4_1.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -fdump-rtl-expand" } */ + +#include <arm_neon.h> + +uint32x2x4_t +test_1 (uint32x2x4_t a, uint32x2x4_t b) +{ + uint32x2x4_t result; + + for (unsigned index = 0; index < 4; ++index) + result.val[index] = a.val[index] + b.val[index]; + + return result; +} + +/* Should not use the stack in expand. */ +/* { dg-final { scan-rtl-dump-not "virtual-stack-vars" "expand" } } */ +/* Should not have to modify the stack pointer. */ +/* { dg-final { scan-assembler-not "\t(add|sub).*sp" } } */ +/* Should not have to store or load anything. */ +/* { dg-final { scan-assembler-not "\t(ld|st)\[rp\]" } } */ |