RISC-V: Refactor the testcases for rvv binop and cmp

This patch would like to refactor the testcases for rvv binop
and cmp after sorts of optimization option passing to testcase.
To fits different optimization option asm dump checks.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: Skip
	m8 as it has different body layout.
	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c: Add build option
	condition when check asm dumps.
	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

6 files changed, 70 insertions, 6 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
index 32d81be..3654b03 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-skip-if "" { *-*-* } { "-mrvv-max-lmul=dynamic" } } */
 #define MAX     10
 
 struct s { struct s *n; } *p;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c
index 10c232f..0715a78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c
@@ -12,5 +12,16 @@ CMP_VI (ne_unsigned_short, unsigned short, n, !=, 15)
 CMP_VI (ne_unsigned_int, unsigned int, n, !=, 15)
 CMP_VI (ne_unsigned_long, unsigned long, n, !=, 15)
 
-/* { dg-final { scan-assembler-times {vmsne\.vi} 16 } } */
+/* { dg-final { scan-assembler-times {vmsne\.vi} 16 { target {
+     any-opts "-mrvv-max-lmul=m1"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vmsne\.vi} 10 { target {
+     any-opts "-mrvv-max-lmul=m2"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vmsne\.vi} 8 { target {
+     any-opts "-mrvv-max-lmul=m4" "-mrvv-max-lmul=m8" "-mrvv-max-lmul=dynamic"
+   } } } } */
+
 /* { dg-final { scan-assembler-not {vmsne\.vv} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c
index 92bea59..3ca8b28 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c
@@ -12,5 +12,16 @@ CMP_VI (ne_unsigned_short, unsigned short, n, !=, -16)
 CMP_VI (ne_unsigned_int, unsigned int, n, !=, -16)
 CMP_VI (ne_unsigned_long, unsigned long, n, !=, -16)
 
-/* { dg-final { scan-assembler-times {vmsne\.vi} 13 } } */
+/* { dg-final { scan-assembler-times {vmsne\.vi} 13 { target {
+     any-opts "-mrvv-max-lmul=m1"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vmsne\.vi} 7 { target {
+     any-opts "-mrvv-max-lmul=m2"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vmsne\.vi} 5 { target {
+     any-opts "-mrvv-max-lmul=m4" "-mrvv-max-lmul=m8" "-mrvv-max-lmul=dynamic"
+   } } } } */
+
 /* { dg-final { scan-assembler-not {vmsne\.vv} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c
index b7a5a43..c6d02ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c
@@ -12,5 +12,16 @@ CMP_VI (eq_unsigned_short, unsigned short, n, ==, 15)
 CMP_VI (eq_unsigned_int, unsigned int, n, ==, 15)
 CMP_VI (eq_unsigned_long, unsigned long, n, ==, 15)
 
-/* { dg-final { scan-assembler-times {vmseq\.vi} 16 } } */
+/* { dg-final { scan-assembler-times {vmseq\.vi} 16 { target {
+     any-opts "-mrvv-max-lmul=m1"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vmseq\.vi} 10 { target {
+     any-opts "-mrvv-max-lmul=m2"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vmseq\.vi} 8 { target {
+     any-opts "-mrvv-max-lmul=m4" "-mrvv-max-lmul=m8" "-mrvv-max-lmul=dynamic"
+   } } } } */
+
 /* { dg-final { scan-assembler-not {vmseq\.vv} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c
index f297ac8..3ef0df5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c
@@ -12,5 +12,16 @@ CMP_VI (eq_unsigned_short, unsigned short, n, ==, -16)
 CMP_VI (eq_unsigned_int, unsigned int, n, ==, -16)
 CMP_VI (eq_unsigned_long, unsigned long, n, ==, -16)
 
-/* { dg-final { scan-assembler-times {vmseq\.vi} 13 } } */
+/* { dg-final { scan-assembler-times {vmseq\.vi} 13 { target {
+     any-opts "-mrvv-max-lmul=m1"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vmseq\.vi} 13 { target {
+     any-opts "-mrvv-max-lmul=m2"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vmseq\.vi} 13 { target {
+     any-opts "-mrvv-max-lmul=m4" "-mrvv-max-lmul=m8" "-mrvv-max-lmul=dynamic"
+   } } } } */
+
 /* { dg-final { scan-assembler-not {vmseq\.vv} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c
index bfc1a68..7289ed9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c
@@ -12,7 +12,26 @@ CMP_VI (le_unsigned_short, unsigned short, n, <=, 15)
 CMP_VI (le_unsigned_int, unsigned int, n, <=, 15)
 CMP_VI (le_unsigned_long, unsigned long, n, <=, 15)
 
-/* { dg-final { scan-assembler-times {vmsle\.vi} 7 } } */
-/* { dg-final { scan-assembler-times {vmsleu\.vi} 9 } } */
+/* { dg-final { scan-assembler-times {vmsle\.vi} 7 { target {
+     any-opts "-mrvv-max-lmul=m1"
+   } } } } */
+/* { dg-final { scan-assembler-times {vmsleu\.vi} 9 { target {
+     any-opts "-mrvv-max-lmul=m1"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vmsle\.vi} 4 { target {
+     any-opts "-mrvv-max-lmul=m2"
+   } } } } */
+/* { dg-final { scan-assembler-times {vmsleu\.vi} 6 { target {
+     any-opts "-mrvv-max-lmul=m2"
+   } } } } */
+
+/* { dg-final { scan-assembler-times {vmsle\.vi} 3 { target {
+     any-opts "-mrvv-max-lmul=m4" "-mrvv-max-lmul=m8" "-mrvv-max-lmul=dynamic"
+   } } } } */
+/* { dg-final { scan-assembler-times {vmsleu\.vi} 5 { target {
+     any-opts "-mrvv-max-lmul=m4" "-mrvv-max-lmul=m4" "-mrvv-max-lmul=dynamic"
+   } } } } */
+
 /* { dg-final { scan-assembler-not {vmsle\.vv} } } */
 /* { dg-final { scan-assembler-not {vmsleu\.vv} } } */