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| author | Maciej W. Rozycki <macro@orcam.me.uk> | 2024-12-25 22:23:39 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@orcam.me.uk> | 2024-12-25 22:23:39 +0000 |
| commit | 6036a1a479154706a3a7c779ee28e74b03357c55 (patch) | |
| tree | 7623333a5a32da5c108b8bcdc5f7b642199d946a /gcc | |
| parent | 3c99ea19d26a2458302c54a33fbd17abfbef787a (diff) | |
| download | gcc-6036a1a479154706a3a7c779ee28e74b03357c55.zip gcc-6036a1a479154706a3a7c779ee28e74b03357c55.tar.gz gcc-6036a1a479154706a3a7c779ee28e74b03357c55.tar.bz2 | |
Alpha: Remove code duplication in block clear trailer
Remove code duplication in the part of `alpha_expand_block_clear' that
handles any aligned trailing part of the block, observing that the two
legs of code only differ by the machine mode and that we already take
the same approach with handling any unaligned prefix earlier on. No
functional change, just code shuffling.
gcc/
* config/alpha/alpha.cc (alpha_expand_block_clear): Fold two
legs of a conditional together.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/alpha/alpha.cc | 41 |
1 files changed, 12 insertions, 29 deletions
diff --git a/gcc/config/alpha/alpha.cc b/gcc/config/alpha/alpha.cc index f196524..58da4a8 100644 --- a/gcc/config/alpha/alpha.cc +++ b/gcc/config/alpha/alpha.cc @@ -4236,40 +4236,23 @@ alpha_expand_block_clear (rtx operands[]) /* If we have appropriate alignment (and it wouldn't take too many instructions otherwise), mask out the bytes we need. */ - if (TARGET_BWX ? words > 2 : bytes > 0) + if ((TARGET_BWX ? words > 2 : bytes > 0) + && (align >= 64 || (align >= 32 && bytes < 4))) { - if (align >= 64) - { - rtx mem, tmp; - HOST_WIDE_INT mask; + machine_mode mode = (align >= 64 ? DImode : SImode); + rtx mem, tmp; + HOST_WIDE_INT mask; - mem = adjust_address (orig_dst, DImode, ofs); - set_mem_alias_set (mem, 0); + mem = adjust_address (orig_dst, mode, ofs); + set_mem_alias_set (mem, 0); - mask = HOST_WIDE_INT_M1U << (bytes * 8); + mask = HOST_WIDE_INT_M1U << (bytes * 8); - tmp = expand_binop (DImode, and_optab, mem, GEN_INT (mask), - NULL_RTX, 1, OPTAB_WIDEN); + tmp = expand_binop (mode, and_optab, mem, GEN_INT (mask), + NULL_RTX, 1, OPTAB_WIDEN); - emit_move_insn (mem, tmp); - return 1; - } - else if (align >= 32 && bytes < 4) - { - rtx mem, tmp; - HOST_WIDE_INT mask; - - mem = adjust_address (orig_dst, SImode, ofs); - set_mem_alias_set (mem, 0); - - mask = HOST_WIDE_INT_M1U << (bytes * 8); - - tmp = expand_binop (SImode, and_optab, mem, GEN_INT (mask), - NULL_RTX, 1, OPTAB_WIDEN); - - emit_move_insn (mem, tmp); - return 1; - } + emit_move_insn (mem, tmp); + return 1; } if (!TARGET_BWX && bytes >= 4) |