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author | GCC Administrator <gccadmin@gcc.gnu.org> | 2024-09-19 00:18:55 +0000 |
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committer | GCC Administrator <gccadmin@gcc.gnu.org> | 2024-09-19 00:18:55 +0000 |
commit | 57faabfbb3e58c66d924fced96c0fd2b5b3fc0c7 (patch) | |
tree | 6b22e363cf791b315d4d215c235214a457f41fbc /gcc | |
parent | 1d1687513400c1b805bf5924f732c21dbf166ae8 (diff) | |
download | gcc-57faabfbb3e58c66d924fced96c0fd2b5b3fc0c7.zip gcc-57faabfbb3e58c66d924fced96c0fd2b5b3fc0c7.tar.gz gcc-57faabfbb3e58c66d924fced96c0fd2b5b3fc0c7.tar.bz2 |
Daily bump.
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 97 | ||||
-rw-r--r-- | gcc/DATESTAMP | 2 | ||||
-rw-r--r-- | gcc/cp/ChangeLog | 18 | ||||
-rw-r--r-- | gcc/jit/ChangeLog | 4 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 77 |
5 files changed, 197 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 55333b6..f5c4db5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,100 @@ +2024-09-18 John David Anglin <danglin@gcc.gnu.org> + + * config/pa/pa.h (GENERAL_REGNO_P): Define. + * config/pa/pa.md: Add SImode and SFmode peephole2 + patterns to generate loads and stores with long + displacements. + +2024-09-18 Jin Ma <jinma@linux.alibaba.com> + + * config/riscv/riscv.md: Change "truncate" to unspec for the Zfa extension on rv32. + +2024-09-18 Richard Biener <rguenther@suse.de> + + * params.opt (vect-force-slp): New param, default 0. + * doc/invoke.texi (--param vect-force-slp): Document. + * tree-vect-loop.cc (vect_analyze_loop_2): When analyzing + without SLP but --param vect-force-slp is 1 fail. + * tree-vect-stmts.cc (vect_analyze_stmt): Fail vectorization + for non-SLP stmts when --param vect-force-slp is 1. + +2024-09-18 Xianmiao Qu <cooper.qu@linux.alibaba.com> + + * config/riscv/riscv.cc (riscv_rtx_costs): Fix the outer_code + when calculating the cost of SET expression. + +2024-09-18 Xianmiao Qu <cooper.qu@linux.alibaba.com> + + * config/riscv/thead.md (*th_extu<mode>4): Fix th.extu + operands exceeding range on rv32. + +2024-09-18 Bohan Lei <garthlei@linux.alibaba.com> + + * config/riscv/vector.md: Allow zero operand for DI variants of + vssubu.vx + +2024-09-18 Jennifer Schmitz <jschmitz@nvidia.com> + + PR tree-optimization/116569 + * match.pd: Guard simplification to trunc_mod with check for + mod optab support. + +2024-09-18 Georg-Johann Lay <avr@gjlay.de> + + PR rtl-optimization/116326 + * reload1.cc (reg_eliminate_1): Initialize from + RELOAD_ELIMINABLE_REGS if defined. + * config/avr/avr.h (RELOAD_ELIMINABLE_REGS): Copy from ELIMINABLE_REGS. + (ELIMINABLE_REGS): Don't mention sub-regnos of the frame pointer. + * doc/tm.texi.in (Eliminating Frame Pointer and Arg Pointer) + <RELOAD_ELIMINABLE_REGS>: Add documentation. + * doc/tm.texi: Rebuild. + +2024-09-18 Georg-Johann Lay <avr@gjlay.de> + + * doc/install.texi (Host/Target specific installation notes for GCC) + [avr]: Update web links to AVR-LibC and AVR Options. + Remove outdated note about Binutils. + +2024-09-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/116585 + * tree-data-ref.cc (split_constant_offset_1): When either + operand is subject to abnormal coalescing do no further + processing. + +2024-09-18 Andrew Pinski <quic_apinski@quicinc.com> + + * tree-ssa-phiopt.cc (cond_if_else_store_replacement): Use + range fors and use one vec for then/else stores instead of 2. + +2024-09-18 Andrew Pinski <quic_apinski@quicinc.com> + + * tree-ssa-phiopt.cc (cond_if_else_store_replacement_1): Add debug dump. + +2024-09-18 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec.md (ssadd<mode>3): Add new pattern for + signed integer vector SAT_ADD. + * config/riscv/riscv-protos.h (expand_vec_ssadd): Add new func + decl for vector ssadd expanding. + * config/riscv/riscv-v.cc (expand_vec_ssadd): Add new func impl + to expand vector ssadd pattern. + +2024-09-18 Michael Meissner <meissner@linux.ibm.com> + + PR target/89213 + * config/rs6000/altivec.md (UNSPEC_VECTOR_SHIFT): New unspec. + (VSHIFT_MODE): New mode iterator. + (vshift_code): New code iterator. + (vshift_attr): New code attribute. + (altivec_<mode>_<vshift_attr>_const): New pattern to optimize + vector long long/int shifts by a constant. + (altivec_<mode>_shift_const): New helper insn to load up a + constant used by the shift operation. + * config/rs6000/predicates.md (vector_shift_constant): New + predicate. + 2024-09-17 Marek Polacek <polacek@redhat.com> PR c++/116534 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 6d5458f..f2530dd 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20240918 +20240919 diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 43f8ae6..9d23925 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,21 @@ +2024-09-18 Patrick Palka <ppalka@redhat.com> + + PR c++/116714 + PR c++/107390 + * pt.cc (dependent_opaque_alias_p): Also return true for a + decltype(lambda) alias. + +2024-09-18 Jason Merrill <jason@redhat.com> + + * call.cc (do_warn_dangling_reference): Return temporary + instead of the call it's passed to. + (maybe_warn_dangling_reference): Adjust diagnostic. + +2024-09-18 Jason Merrill <jason@redhat.com> + + PR c++/115361 + * call.cc (do_warn_dangling_reference): Check is_empty_class. + 2024-09-17 Marek Polacek <polacek@redhat.com> PR c++/116741 diff --git a/gcc/jit/ChangeLog b/gcc/jit/ChangeLog index 66704b2..37a7f11 100644 --- a/gcc/jit/ChangeLog +++ b/gcc/jit/ChangeLog @@ -1,3 +1,7 @@ +2024-09-18 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org> + + * libgccjit.h: Include <sys/types.h> + 2024-09-09 David Malcolm <dmalcolm@redhat.com> PR other/116613 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9d9c049..6c75524 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,80 @@ +2024-09-18 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/sat_s_add-4.c: Update test for int64_t + instead of int8_t. + +2024-09-18 Patrick Palka <ppalka@redhat.com> + + PR c++/116714 + PR c++/107390 + * g++.dg/cpp2a/lambda-uneval18.C: New test. + +2024-09-18 Jin Ma <jinma@linux.alibaba.com> + + * gcc.target/riscv/zfa-fmovh-fmovp-bug.c: New test. + +2024-09-18 Xianmiao Qu <cooper.qu@linux.alibaba.com> + + * gcc.target/riscv/xtheadbb-extu-4.c: New. + +2024-09-18 Bohan Lei <garthlei@linux.alibaba.com> + + * gcc.target/riscv/rvv/base/vssubu-1.c: New test. + * gcc.target/riscv/rvv/base/vssubu-2.c: New test. + +2024-09-18 Jason Merrill <jason@redhat.com> + + * g++.dg/warn/Wdangling-reference1.C: Adjust diagnostic. + +2024-09-18 Jason Merrill <jason@redhat.com> + + PR c++/115361 + * g++.dg/ext/attr-no-dangling6.C + * g++.dg/ext/attr-no-dangling7.C + * g++.dg/ext/attr-no-dangling8.C + * g++.dg/ext/attr-no-dangling9.C + * g++.dg/warn/Wdangling-reference1.C + * g++.dg/warn/Wdangling-reference2.C + * g++.dg/warn/Wdangling-reference3.C: Make classes non-empty. + * g++.dg/warn/Wdangling-reference23.C: New test. + +2024-09-18 Jennifer Schmitz <jschmitz@nvidia.com> + + PR tree-optimization/116569 + * gcc.dg/torture/pr116569.c: New test. + +2024-09-18 Georg-Johann Lay <avr@gjlay.de> + + PR rtl-optimization/116326 + * gcc.target/avr/torture/lra-pr116324.c: New test. + * gcc.target/avr/torture/lra-pr116325.c: New test. + +2024-09-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/116585 + * gcc.dg/torture/pr116585.c: New testcase. + +2024-09-18 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: Add test + data for vector ssadd. + * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper + macros. + * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c: New test. + * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c: New test. + * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c: New test. + * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c: New test. + * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-1.c: New test. + * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-2.c: New test. + * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-3.c: New test. + * gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-4.c: New test. + +2024-09-18 Michael Meissner <meissner@linux.ibm.com> + + PR target/89213 + * gcc.target/powerpc/pr89213.c: New test. + * gcc.target/powerpc/vec-rlmi-rlnm.c: Update instruction count. + 2024-09-17 Marek Polacek <polacek@redhat.com> PR c++/116741 |