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| author | Lulu Cheng <chenglulu@loongson.cn> | 2023-10-23 09:07:32 +0800 |
|---|---|---|
| committer | Lulu Cheng <chenglulu@loongson.cn> | 2023-10-23 09:26:43 +0800 |
| commit | 5697ed0327f23d2e2ec4f7beec3b3d02f463173c (patch) | |
| tree | 04137f9d1a1bb53e5972e67b898ea39ef6f09974 /gcc | |
| parent | f08ca5903c7a02b450b93143467f70b9fd8e0085 (diff) | |
| download | gcc-5697ed0327f23d2e2ec4f7beec3b3d02f463173c.zip gcc-5697ed0327f23d2e2ec4f7beec3b3d02f463173c.tar.gz gcc-5697ed0327f23d2e2ec4f7beec3b3d02f463173c.tar.bz2 | |
LoongArch: Define macro CLEAR_INSN_CACHE.
LoongArch's microstructure ensures cache consistency by hardware.
Due to out-of-order execution, "ibar" is required to ensure the visibility of the
store (invalidated icache) executed by this CPU before "ibar" (to the instance).
"ibar" will not invalidate the icache, so the start and end parameters are not Affect
"ibar" performance.
gcc/ChangeLog:
* config/loongarch/loongarch.h (CLEAR_INSN_CACHE): New definition.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/loongarch/loongarch.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h index da3ec2a..c72fc51 100644 --- a/gcc/config/loongarch/loongarch.h +++ b/gcc/config/loongarch/loongarch.h @@ -1231,3 +1231,8 @@ struct GTY (()) machine_function (TARGET_HARD_FLOAT_ABI ? (TARGET_DOUBLE_FLOAT_ABI ? 8 : 4) : 0) #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN) + +/* LoongArch maintains ICache/DCache coherency by hardware, + we just need "ibar" to avoid instruction hazard here. */ +#undef CLEAR_INSN_CACHE +#define CLEAR_INSN_CACHE(beg, end) __builtin_loongarch_ibar (0) |